# US 2013/0154077 A1 · Chip package and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154077 A1 - Document ID: US20130154077A1 - Status: Published application - Kind: A1 - Application number: 13/720,649 - Filed: 2012-12-19 - Published: 2013-06-20 - Earliest claimed: 2011-12-19 - Assignees: Xintec Inc. - Inventors: Kuo-Hua LIU; Yi-Ming CHANG; Hsi-Chien LIN - Web page: https://patentgrep.com/patent/US20130154077A1 ## CPC - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10F 39/026: {Wafer-level processing} - H10F 39/804: {Containers or encapsulations} - H10W 72/00: Interconnections or connectors in packages - H10W 74/014: {using batch processing} - H10W 76/60: Seals - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad. ## Claims ### Claim 1 A chip package, comprising: a substrate having a first surface and a second surface; a device region formed in the substrate or disposed on the substrate; a dielectric layer disposed on the first surface of the substrate; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between an upper surface of the planar layer and an upper surface of the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface of the substrate; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad. ### Claim 2 (depends on 1) The chip package as claimed in claim 1, wherein the first spacer layer directly contacts with the planar layer and does not contact with the dielectric layer or the substrate. ### Claim 3 (depends on 1) The chip package as claimed in claim 1, wherein the first spacer layer, the transparent substrate, and the planar layer together surround a substantially closed cavity on the device region, and the second spacer layer surrounds the first spacer layer. ### Claim 4 (depends on 3) The chip package as claimed in claim 3, further comprising an optical element disposed on the planar layer and located in the cavity. ### Claim 5 (depends on 4) The chip package as claimed in claim 4, wherein the optical element comprises a light filter layer, a color filter layer, a polarization layer, a lens, a light shielding layer, or combinations thereof. ### Claim 6 (depends on 1) The chip package as claimed in claim 1, wherein a height of the first spacer layer is larger than a height of the second spacer layer. ### Claim 7 (depends on 1) The chip package as claimed in claim 1, wherein the first spacer layer directly contacts with the second spacer layer. ### Claim 8 (depends on 1) The chip package as claimed in claim 1, wherein the first spacer layer does not directly contact with the second spacer layer. ### Claim 9 (depends on 1) The chip package as claimed in claim 1, wherein the materials of the first spacer layer and the second spacer layer are the same. ### Claim 10 A chip package, comprising: a substrate having a first surface and a second surface; a device region formed in the substrate or disposed on the substrate; a dielectric layer disposed on the first surface of the substrate; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer; a transparent substrate disposed on the first surface of the substrate; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate, wherein the second spacer layer comprises a main portion and an extending portion, and the extending portion covers a surface of the main portion and extends onto an opening of the dielectric layer to contact with the conducting pad. ### Claim 11 (depends on 10) The chip package as claimed in claim 10, wherein the extending portion of the second spacer layer covers a side surface of the main portion. ### Claim 12 (depends on 11) The chip package as claimed in claim 11, wherein the extending portion directly contacts with the transparent substrate. ### Claim 13 (depends on 12) The chip package as claimed in claim 12, wherein the extending portion directly contacts with the first spacer layer. ### Claim 14 (depends on 10) The chip package as claimed in claim 10, wherein the materials of the main portion and the extending portion of the second spacer layer are the same. ### Claim 15 (depends on 10) The chip package as claimed in claim 10, wherein the materials of the first spacer layer and the second spacer layer are the same. ### Claim 16 (depends on 10) The chip package as claimed in claim 10, wherein the first spacer layer, the transparent substrate, and the planar layer together surround a substantially closed cavity on the device region, and the second spacer layer surrounds the first spacer layer. ### Claim 17 A method for forming a chip package, comprising: providing a substrate having a first surface and a second surface, wherein a device region is formed in the substrate or disposed on the substrate, a dielectric layer is disposed in the first surface of the substrate, at least one conducting pad is disposed in the dielectric layer and electrically connected to the device region, and a planar layer is disposed on the dielectric layer; providing a transparent substrate; forming a patterned spacer layer on a surface of the transparent substrate, wherein the patterned spacer layer comprises a first spacer layer and a second spacer layer, the first spacer layer surrounds a region on the transparent substrate, and the second spacer layer surrounds the first spacer layer; disposing a spacer layer material on an upper surface of the second spacer layer; and disposing the substrate on the transparent substrate, wherein the first spacer layer directly contacts with the planar layer, and the spacer layer material bonds with the dielectric layer and fills an opening of the dielectric layer to contact with the conducting pad. ### Claim 18 (depends on 17) The method for forming a chip package as claimed in claim 17, wherein the step of disposing the spacer layer material comprises: disposing a mask on the patterned spacer layer, wherein the mask has a hole exposing the upper surface of the second spacer layer; applying a spacer layer coating on the mask, wherein a portion of the spacer layer coating fills the hole of the mask to directly contact with the upper surface of the second spacer layer; and removing the mask such that the spacer layer material is left on the upper surface of the second spacer layer. ### Claim 19 (depends on 17) The method for forming a chip package as claimed in claim 17, before the step of disposing the substrate on the transparent substrate is performed, further comprising performing a curing process to the spacer layer material. ### Claim 20 (depends on 19) The method for forming a chip package as claimed in claim 19, wherein the curing process comprises performing a soft bake process, a light illumination process, or combinations thereof to the spacer layer material. ### Claim 21 (depends on 19) The method for forming a chip package as claimed in claim 19, further comprising performing a hard bake process to the patterned spacer layer and the spacer layer material. ### Claim 22 (depends on 17) The method for forming a chip package as claimed in claim 17, after the step of disposing the substrate on the transparent substrate is performed, further comprising performing a curing process to the spacer layer material. ### Claim 23 (depends on 22) The method for forming a chip package as claimed in claim 22, wherein the curing process comprises performing a soft bake process, a light illumination process, or combinations thereof to the spacer layer material. ### Claim 24 (depends on 22) The method for forming a chip package as claimed in claim 22, further comprising performing a hard bake process to the patterned spacer layer and the spacer layer material. ### Claim 25 (depends on 17) The method for forming a chip package as claimed in claim 17, further comprising performing a dicing process along a plurality of predetermined scribe lines of the substrate to form a plurality of chip packages. ### Claim 26 (depends on 25) The method for forming a chip package as claimed in claim 25, wherein the second spacer layer comprises a recess, a portion of the spacer layer material extends into the recess, and the recess is located on one of the predetermined scribe lines.