# US 2013/0154076 A1 · Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect

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- Number: US 2013/0154076 A1
- Document ID: US20130154076A1
- Status: Published application
- Kind: A1
- Application number: 13/766,646
- Filed: 2013-02-13
- Published: 2013-06-20
- Earliest claimed: 2010-09-14
- Assignees: STATS ChipPAC, Ltd.
- Inventors: Zigmund R. Camacho; Dioscoro A. Merilo; Henry D. Bathan; Emmanuel A. Espiritu
- Web page: https://patentgrep.com/patent/US20130154076A1

## CPC

- H10W 70/40: Leadframes
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 2203/0384: Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
- H10W 70/042: {Etching}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07554: {changes in dispositions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

## Claims

### Claim 1

A semiconductor device, comprising:
a first substrate;
a first semiconductor die disposed over the first substrate;
a second substrate including a plurality of base leads extending from the second substrate, wherein the second substrate is disposed over the first substrate and first semiconductor die; and
an etch-resistant material formed over a surface of the second substrate opposite the base leads.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further including an encapsulant deposited over the first semiconductor die and first substrate.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further including an opening in the second substrate for depositing the encapsulant.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further including a second semiconductor die or component disposed over the first semiconductor die.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the second substrate outside the etch-resistant material is removed to electrically isolate the base leads.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further including a second semiconductor die disposed over the base leads.

### Claim 7

A semiconductor device, comprising:
a first substrate;
a first semiconductor die disposed over the first substrate; and
a second substrate including a plurality of base leads extending from the second substrate, wherein the second substrate is disposed over the first semiconductor die with the base leads extending to the first substrate.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further including an encapsulant deposited over the first semiconductor die and first substrate.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, further including a second semiconductor die or component disposed over the first semiconductor die.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, further including a plurality of stacked semiconductor devices electrically connected through the base leads and first substrate.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, further including an etch-resistant material formed over a surface of the second substrate opposite the base leads.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein a portion of the second substrate is removed to electrically isolate the base leads.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, further including a second semiconductor die disposed over the base leads.

### Claim 14

A semiconductor device, comprising:
a substrate;
a first semiconductor die disposed over the substrate;
a plurality of base leads disposed around the first semiconductor die and electrically connected to the substrate; and
an etch-resistant material formed over a surface of the base leads opposite the substrate.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further including an encapsulant deposited over the first semiconductor die and substrate.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further including a second semiconductor die or component disposed over the first semiconductor die.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, further including an interconnect structure formed over a surface of the substrate opposite the base leads.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, further including a second semiconductor die disposed over the base leads.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, further including an underfill material deposited between the first semiconductor die and substrate.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, further including a plurality of stacked semiconductor devices electrically connected through the base leads and substrate.

### Claim 21

A semiconductor device, comprising:
a first substrate;
a first semiconductor die disposed over the first substrate; and
a second substrate including a plurality of base leads disposed over the first semiconductor die and first substrate.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, further including an encapsulant deposited over the first semiconductor die and first substrate.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, further including an opening in the second substrate for depositing the encapsulant.

### Claim 24 (depends on 21)

The semiconductor device of claim 21, further including a second semiconductor die or component disposed over the first semiconductor die.

### Claim 25 (depends on 21)

The semiconductor device of claim 21, wherein a portion of the second substrate is removed to electrically isolate the base leads.