# US 2013/0154075 A1 · Semiconductor device

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- Number: US 2013/0154075 A1
- Document ID: US20130154075A1
- Status: Published application
- Kind: A1
- Application number: 13/716,985
- Filed: 2012-12-17
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Renesas Electronics Corporation
- Inventors: Koichi KANEMOTO
- Web page: https://patentgrep.com/patent/US20130154075A1

## CPC

- H10W 90/811: {Multiple chips on leadframes}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/427: {Bent parts}
- H10W 70/465: {Bumps or wires}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/07554: {changes in dispositions}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/732: {between stacked chips}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.

## Claims

### Claim 1

A semiconductor device comprising:
a die pad having an upper surface and a lower surface opposite to the upper surface;
a plurality of leads arranged around the die pad;
a first semiconductor chip having a first main surface, a first semiconductor element formed on the first main surface, a plurality of first electrode pads formed on the first main surface and electrically connected to the first semiconductor element, a first protective film formed on the first main surface such that the plurality of first electrode pads are exposed, and a first rear surface opposite to the first main surface, the first semiconductor chip being mounted on the die pad such that the first rear surface is opposed to the upper surface of the die pad;
a second semiconductor chip having a second main surface, a second semiconductor element formed on the second main surface, a plurality of second electrode pads formed on the second main surface and electrically connected to the second semiconductor element, a second protective film formed on the second main surface such that the plurality of second electrode pads are exposed, and a second rear surface opposite to the second main surface, the second semiconductor chip being mounted on the first semiconductor chip such that the second rear surface is opposed to the first main surface of the first semiconductor chip;
a plurality of first conductive members electrically connecting the plurality of first electrode pads with the plurality of leads, respectively;
a plurality of second conductive members electrically connecting the plurality of first electrode pads with the plurality of second electrode pads, respectively; and
a sealing member sealing the die pad, the first semiconductor chip, the second semiconductor chip, the plurality of first conductive members and the plurality of second conductive members such that the lower surface of the die pad is exposed,
wherein the second protective film is comprised of a polymeric material containing benzocyclobutene in a backbone thereof as an organic monomer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein a wiring layer is further formed on the second main surface of the second semiconductor chip, and
wherein the second protective film is formed on the wiring layer such that one portion of the wiring layer is exposed.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein a third semiconductor chip is further stacked on the second semiconductor chip,
wherein the second electrode pads of the second semiconductor chip are formed at positions overlapped with the third semiconductor chip when seen in a plan view,
wherein one portion of the wiring layer of the second semiconductor chip is formed at a position not overlapped with the third semiconductor chip when seen in a plan view, and
wherein the second conductive members are electrically connected to the second electrode pads through the wiring layer.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3,
wherein one portion of the sealing member is disposed on the third semiconductor chip.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein the sealing member is comprised of epoxy-based thermosetting resin.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein an outside size of the die pad is larger than an outside size of the first semiconductor chip when seen in a plan view, and
wherein the die pad is electrically connected to the first electrode pads of the first semiconductor chip through the first conductive members.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein an outside size of the die pad is smaller than an outside size of the first semiconductor chip when seen in a plan view.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1,
wherein the die pad is supported by a plurality of suspension leads, and
wherein a bar lead is formed between the adjacent suspension leads among the plurality of suspension leads and between the die pad and the plurality of leads when seen in a plan view.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8,
wherein the bar lead is disposed at a height between a height at which the die pad is positioned and a height at which the lead is positioned when seen in a cross-sectional view.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1,
wherein a lower surface of each of the plurality of leads is exposed from a lower surface of the sealing member.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1,
wherein on the first main surface of the first semiconductor chip, the plurality of first electrode pads are formed along each of four sides of the first main surface, and the plurality of leads are arranged around the four sides of the first main surface.