# US 2013/0154074 A1 · Semiconductor stack packages and methods of fabricating the same

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- Number: US 2013/0154074 A1
- Document ID: US20130154074A1
- Status: Published application
- Kind: A1
- Application number: 13/615,840
- Filed: 2012-09-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: SK hynix Inc.
- Inventors: Tac Keun OH
- Web page: https://patentgrep.com/patent/US20130154074A1

## CPC

- H10W 90/00: Package configurations
- H10W 74/014: {using batch processing}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07254: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.

## Claims

### Claim 1

A semiconductor stack package, comprising:
an interposer;
a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer;
a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack; and
an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer.

### Claim 2 (depends on 1)

The semiconductor stack package of claim 1, further comprising:
a first through electrode penetrating the interposer;
a second through electrode that penetrates the first semiconductor chips to electrically connect the first semiconductor chips to the first through electrode; and
a third through electrode that penetrates the second semiconductor chip to electrically connect the first through electrode to the external electrode.

### Claim 3

A semiconductor stack package, comprising:
an interposer in which a first through electrode is inserted;
a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer;
a second through electrode that penetrates the semiconductor chip stack to be electrically connected to the first through electrode;
a second semiconductor chip on a bottom surface of the interposer; and
a third through electrode that penetrates the second semiconductor chip to be electrically connected to the first through electrode.

### Claim 4 (depends on 3)

The semiconductor stack package of claim 3, further comprising a protection layer covering the semiconductor chip stack.

### Claim 5 (depends on 3)

The semiconductor stack package of claim 3, wherein each of the plurality of first semiconductor chips includes a memory chip.

### Claim 6 (depends on 3)

The semiconductor stack package of claim 3, wherein the second semiconductor chip includes a logic chip.

### Claim 7 (depends on 3)

The semiconductor stack package of claim 3, further comprising a protection layer covering the second semiconductor chip.

### Claim 8 (depends on 7)

The semiconductor stack package of claim 7, wherein the protection layer covers sidewalls of the second semiconductor chip and to expose a top surface of the second semiconductor chip opposite to the interposer.

### Claim 9 (depends on 3)

The semiconductor stack package of claim 3, further comprising an external electrode electrically connected to the third through electrode.

### Claim 10

A method of fabricating a semiconductor stack package, the method comprising:
vertically stacking a plurality of first semiconductor chips on a top surface of an interposer to form a semiconductor chip stack; and
stacking a second semiconductor chip on a bottom surface of the interposer opposite to the semiconductor chip stack.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a first through electrode that penetrates a body of the interposer,
wherein one end of the first through electrode is exposed at the top surface of the interposer to constitute a first contact portion, and an other end of the first through electrode is exposed at the bottom surface of the interposer to constitute a second contact portion.

### Claim 12 (depends on 11)

The method of claim 11, wherein the semiconductor chip stack is formed to include a second through electrode that penetrates the plurality of first semiconductor chips to electrically connect the first semiconductor chips to each other, and the second through electrode is electrically connected to the first through electrode.

### Claim 13 (depends on 11)

The method of claim 11, wherein the second semiconductor chip is formed to include a second through electrode that penetrates a body of the second semiconductor chip, and the second through electrode is electrically connected to the first through electrode.

### Claim 14 (depends on 13)

The method of claim 13, further comprising attaching an external electrode to the second through electrode.

### Claim 15 (depends on 10)

The method of claim 10, wherein the interposer is a substrate including silicon material.