# US 2013/0154073 A1 · Method of forming a semiconductor device and leadframe therefor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0154073 A1
- Document ID: US20130154073A1
- Status: Published application
- Kind: A1
- Application number: 13/327,032
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Semiconductor Components Industries, LLC
- Inventors: Harold L. Massie; Phillip Celaya; David F. Moeller; Mark Randol
- Web page: https://patentgrep.com/patent/US20130154073A1

## CPC

- H10W 70/466: {Tape carriers or flat leads}
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/07653: {changes in shapes}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/652: {comprising metals or metalloids, e.g. silver}
- H10W 72/655: {of outermost layers of multilayered strap connectors, e.g. material of a coating}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/886: {Die-attach connectors and strap connectors}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/763: {between laterally-adjacent chips}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

## Claims

### Claim 1

A semiconductor device comprising:
a leadframe for receiving semiconductor die, the leadframe having a first die attachment area for receiving a first semiconductor die, having a second die attachment area for receiving a second semiconductor die;
the first semiconductor die having a first MOS transistor, the first MOS transistor having a source mechanically attached to the first die attachment area;
the second semiconductor die having a second MOS transistor, the second MOS transistor having a drain mechanically attached to the second die attachment area; and
a connection clip mechanically and electrically connected to the drain of the first MOS transistor, to the source of the second MOS transistor, wherein a first portion of the connection clip extends to attach to both the first and second semiconductor die and wherein a second portion of the connection clip extends away from the first portion to provide an electrical connection to the drain of the first MOS transistor, to the source of the second MOS transistor.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 further including the leadframe having a lead connection area wherein the second portion of the connection clip extends to the lead connection area and makes electrical and mechanical connection to the lead connection area.

### Claim 3 (depends on 1)

The semiconductor device of claim 1 wherein the first and second die attachment areas are substantially co-planar to each other.

### Claim 4 (depends on 1)

The semiconductor device of claim 1 wherein the leadframe further includes a third die attachment area.

### Claim 5 (depends on 4)

The semiconductor device of claim 4 further including a third semiconductor die attached to the third die attachment area, the third semiconductor die having a first electrical connection to a gate of the first MOS transistor and a second electrical connection to a gate of the second MOS transistor.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 wherein the second portion of the connection clip extends at a first angle away from the first portion of the connection clip.

### Claim 7 (depends on 1)

The semiconductor device of claim 1 wherein the first portion of the connection clip has a first connection pad attached to the drain of the first semiconductor die and a second connection pad attached to the source of the second semiconductor die wherein the first connection pad overlies the drain of the first semiconductor die and the second connection pad overlies the source of the second semiconductor die.

### Claim 8 (depends on 7)

The semiconductor device of claim 7 wherein the first connection pad and the second connection pad extend respective first and second distances from a surface of the first portion of the connection clip and wherein the second portion of the connection clip extends a third distance away from the first portion of the connection clip wherein the third distance is greater than either of the first or second distances.

### Claim 9 (depends on 1)

The semiconductor device of claim 1 wherein the first and second die attachment areas of the leadframe have one of leads extending from the first and second die attachment areas or half-etched pads extending from the first and second die attachment areas.

### Claim 10 (depends on 9)

The semiconductor device of claim 9 further including a third die attachment area and a third semiconductor die attached thereto, the third semiconductor die have a first electrical connection to a gate of the first MOS transistor, a second electrical connection to a gate of the second MOS transistor, and a third electrical connection to a lead of the leadframe to receive a signal from external to the semiconductor device.

### Claim 11 (depends on 1)

The semiconductor device of claim 1 further including an encapsulant covering portions of the connection clip, the first and second semiconductor die, and a portion of the leadframe.

### Claim 12

A method of forming a connection clip for interconnecting a plurality of semiconductor die comprising:
forming a first portion of the connection clip having first and second surfaces that extend co-parallel in a first direction;
forming a first connection pad on the first surface, the first connection pad having an area for electrically and mechanically connecting to a first semiconductor die;
forming a second connection pad on the first surface, the second connection pad having an area for electrically and mechanically connecting to a second semiconductor die wherein the connection clip also forms an electrical connection between the first and second connection pads; and
forming a second portion of the connection clip extending in a plane and at an angle away from the first portion of the connection clip including forming the second portion of the connection clip electrically connected to the first and second connection pads.

### Claim 13 (depends on 12)

The method of claim 12 including forming the connection clip from one continuous piece of metal.

### Claim 14 (depends on 12)

The method of claim 12 wherein forming the second portion of the connection clip includes forming the second portion of the connection clip to extend a distance from the first surface of the connection clip that is greater than a distance the first and second connection pads extend from the first surface.

### Claim 15 (depends on 12)

The method of claim 12 further including forming the first portion of the connection clip to have a first region formed to have a larger area than a second region of the first portion.

### Claim 16

A method of forming a semiconductor package comprising:
forming a leadframe having a first die attachment area for mechanically attaching to a first current carrying electrode of a first transistor, having a second die attachment area for mechanically attaching to a first current carrying electrode of a second transistor; and
forming the semiconductor package with a connection clip configured to electrically couple a second current carrying electrode of the first and second transistors to a terminal of the semiconductor package.

### Claim 17 (depends on 16)

The method of claim 16 further including forming the first and second die attachment areas to be substantially co-planar.

### Claim 18 (depends on 16)

The method of claim 16 further including forming the semiconductor package having a source of the first transistor attached to the first die attachment area, a drain of the second transistor attached to the second die attachment area, and the connection clip electrically attached to a drain of the first transistor and to a source of the second transistor wherein a portion of the connection clip provides a common electrical connection to the source of the first transistor and to drain of the second transistor.

### Claim 19 (depends on 16)

The method of claim 16 further including forming the leadframe having a third die attachment area for mechanically attaching to a third semiconductor die that is different from the first and second transistors.

### Claim 20 (depends on 19)

The method of claim 19 further including forming the leadframe having a connection area for attaching to the connection clip wherein the connection clip electrically couples the second current carrying electrode of the first and second transistors to the connection area.