# US 2013/0154069 A1 · Semiconductor package

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- Number: US 2013/0154069 A1
- Document ID: US20130154069A1
- Status: Published application
- Kind: A1
- Application number: 13/584,143
- Filed: 2012-08-13
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Samsung Electro-Mechanics Co., Ltd.
- Inventors: Tae Hoon Kim; Seog Moon Choi
- Web page: https://patentgrep.com/patent/US20130154069A1

## CPC

- H10W 70/442: {of multiple leadframes in a single chip}
- H10W 40/778: {in encapsulations}
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is a semiconductor package, including: a first heat dissipation substrate; a first lead frame that is formed on the first heat dissipation substrate by patterning; a first semiconductor device formed on the first lead frame; a second semiconductor device that is stacked on the first semiconductor device; a second lead frame that is patterned and bonded to the second semiconductor device; and a second heat dissipation substrate formed on the first lead frame.

## Claims

### Claim 1

A semiconductor package comprising:
a first heat dissipation substrate;
a first lead frame that is formed on the first heat dissipation substrate by patterning;
a first semiconductor device formed on the first lead frame;
a second semiconductor device that is stacked on the first semiconductor device;
a second lead frame that is patterned and bonded to the second semiconductor device; and
a second heat dissipation substrate formed on the first lead frame.

### Claim 2 (depends on 1)

The semiconductor package as set forth in claim 1, wherein the first semiconductor device is a power device.

### Claim 3 (depends on 1)

The semiconductor package as set forth in claim 1, wherein the first semiconductor device is an insulated gate bipolar transistor (IGBT).

### Claim 4 (depends on 1)

The semiconductor package as set forth in claim 1, wherein the second semiconductor device is a control device.

### Claim 5 (depends on 1)

The semiconductor package as set forth in claim 1, wherein the second semiconductor device is a diode.

### Claim 6 (depends on 1)

The semiconductor package as set forth in claim 1, further comprising a housing that surrounds both sides of the first heat dissipation substrate and the second heat dissipation substrate to block inner space formed by the first heat dissipation substrate and the second heat dissipation substrate from the outside.

### Claim 7 (depends on 1)

The semiconductor package as set forth in claim 1, further comprising a first spacer formed between the first semiconductor device and the second lead frame.

### Claim 8 (depends on 1)

The semiconductor package as set forth in claim 1, further comprising an insulating resin filled in an inner space formed by the first heat dissipation substrate and the second heat dissipation substrate.

### Claim 9

A semiconductor package comprising:
a first heat dissipation substrate;
a first lead frame that is formed on the first heat dissipation substrate by patterning;
a first semiconductor device formed on the first lead frame;
a second semiconductor device that is stacked on the first semiconductor device;
a second lead frame that is patterned and bonded to the second semiconductor device;
a second heat dissipation substrate formed on the first lead frame;
a third lead frame that is formed on the second heat dissipation substrate by patterning;
a third semiconductor device formed on the third lead frame;
a fourth semiconductor device that is stacked on the third semiconductor device;
a fourth lead frame that is patterned and bonded to the fourth semiconductor device; and
a third heat dissipation substrate formed on the fourth lead frame.

### Claim 10 (depends on 9)

The semiconductor package as set forth in claim 9, further comprising a housing that surrounds both sides of the first through third heat dissipation substrates so as to block inner space formed by the first through third heat dissipation substrates from the outside.

### Claim 11 (depends on 9)

The semiconductor package as set forth in claim 9, further comprising a first spacer formed between the first semiconductor device and the second lead frame.

### Claim 12 (depends on 9)

The semiconductor package as set forth in claim 9, further comprising a second spacer formed between the third lead frame and the fourth semiconductor device.

### Claim 13 (depends on 9)

The semiconductor package as set forth in claim 9, further comprising a first insulating resin filled in an inner space formed by the first heat dissipation substrate and the second heat dissipation substrate.

### Claim 14 (depends on 9)

The semiconductor package as set forth in claim 9, further comprising a second insulating resin filled in an inner space formed by the second heat dissipation substrate and the third heat dissipation substrate.

### Claim 15 (depends on 9)

The semiconductor package as set forth in claim 9, wherein the second heat dissipation substrate further includes a through via.

### Claim 16 (depends on 15)

The semiconductor package as set forth in claim 15, wherein the through via electrically connects the second lead frame to the third lead frame.

### Claim 17 (depends on 9)

The semiconductor package as set forth in claim 9, wherein the first semiconductor device and the fourth semiconductor device are power devices.

### Claim 18 (depends on 9)

The semiconductor package as set forth in claim 9, wherein the first semiconductor device and the fourth semiconductor device are insulated gate bipolar transistors (IGBTs).

### Claim 19 (depends on 9)

The semiconductor package as set forth in claim 9, wherein the second semiconductor device and the third semiconductor device are control devices.

### Claim 20 (depends on 9)

The semiconductor package as set forth in claim 9, wherein the second semiconductor device and the third semiconductor device are diodes.
