# US 2013/0154068 A1 · Packaged leadless semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154068 A1 - Document ID: US20130154068A1 - Status: Published application - Kind: A1 - Application number: 13/326,636 - Filed: 2011-12-15 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Freescale Semiconductor, Inc. - Inventors: Audel A. Sanchez; Fernando A. Santos; Lakshminarayan Viswanathan - Web page: https://patentgrep.com/patent/US20130154068A1 ## CPC - H10W 74/01: Manufacture or treatment - H10W 20/0698: {Local interconnections} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/778: {in encapsulations} - H10W 70/421: {Shapes or dispositions} - H10W 70/427: {Bent parts} - H10W 70/465: {Bumps or wires} - H10W 72/0198: {batch processes} - H10W 72/075: {of bond wires} - H10W 72/07554: {changes in dispositions} - H10W 72/534: {being rectangular} - H10W 72/5366: {the bond wires having kinks} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/951: {Materials of bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/811: {Multiple chips on leadframes} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32). ## Claims ### Claim 1 A packaged leadless semiconductor device comprising: a heat sink flange having an upper surface and a lower surface spaced apart by a flange thickness; a semiconductor die physically coupled to said upper surface of said heat sink flange; a frame structure having a perimeter that defines a cavity and terminal pads surrounding said cavity, each of said terminal pads including a first surface and a second surface, said first surface being spaced apart from said second surface by a distance that is at greater than said flange thickness, and said heat sink flange is positioned in said cavity such that said lower surface of said heat sink flange and said second surface of each of said terminal pads are in coplanar alignment, and at least a portion of said first surface of said each of said terminal pads overlies said upper surface of said heat sink flange; interconnects electrically connecting said semiconductor die with said first surface of said terminal pads; and an encapsulant substantially encasing said frame structure, said flange, said semiconductor die, and said interconnects with at least said lower surface of said flange and said second surface of said each of said terminal pads remaining exposed from said encapsulant. ### Claim 2 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said first surface is spaced apart from said upper surface of said heat sink flange by a gap, and said semiconductor device further comprises a dielectric material residing in said gap. ### Claim 3 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said each of said terminal pads comprises a folded arrangement having a first section, a second section, and a connector section interconnecting said first and second sections, said first surface being formed on a top side of said first section, and said second surface being formed on an underside of said second section. ### Claim 4 (depends on 3) A packaged leadless semiconductor device as claimed in claim 3 wherein said connector section is spaced apart from a lateral sidewall of said heat sink flange by a gap, and said semiconductor device further comprises a dielectric material residing in said gap. ### Claim 5 (depends on 3) A packaged leadless semiconductor device as claimed in claim 3 wherein said second section is outwardly laterally displaced away from said heat sink flange relative to said first section. ### Claim 6 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said frame structure is pre-formed with bent ones of said terminal pads. ### Claim 7 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said flange thickness is a first thickness, and said upper surface of said heat sink flange comprises: a first portion having said upper surface and said lower surface, said upper surface of said first portion being spaced apart from said lower surface by said first thickness; and a second portion having said upper surface and said lower surface, said upper surface of said second portion being spaced apart from said lower surface by a second thickness that is greater than said first thickness, said lower surface of said second portion being coplanar with said lower surface of said first portion, and said at least a portion of said first surface of said each of said terminal pads overlies said upper surface of said first portion of said heat sink flange. ### Claim 8 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said flange thickness of said heat sink flange is at least thirty mils. ### Claim 9 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said semiconductor die is coupled to said heat sink flange using a high temperature die attach process. ### Claim 10 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said encapsulant is a molding compound encapsulant covering said flange, said frame structure, said semiconductor die, and said interconnects. ### Claim 11 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said encapsulant comprises: an insulator frame surrounding said frame structure and said heat sink flange; and a cap coupled with said insulator frame, said cap including an interior volume to provide an air cavity in which said semiconductor die resides. ### Claim 12 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein said terminal pads of said frame structure includes a connector section interposed between said first and second surfaces, said connector section having notches formed therein, and said encapsulant is a molding compound encapsulant configured to fill said notches to secure said molding compound encapsulant to said frame structure. ### Claim 13 (depends on 1) A packaged leadless semiconductor device as claimed in claim 1 wherein at least one of said upper and lower surfaces and a lateral sidewall of said heat sink flange includes lock features formed therein, and said encapsulant is a molding compound encapsulant configured to fill said lock features to secure said molding compound encapsulant to said heat sink flange. ### Claim 14 A method of packaging a semiconductor die comprising: providing a heat sink flange having an upper surface and a lower surface spaced apart by a flange thickness; attaching said semiconductor die to said upper surface of said flange; providing a frame structure having a perimeter that defines a cavity and terminal pads surrounding said cavity, said frame structure being pre-formed to include bent ones of said terminal pads, each of said terminal pads including a first surface and a second surface, said first surface being spaced apart from said second surface by a distance that is greater than said flange thickness; mechanically staking said frame structure to said heat sink flange such that at least a portion of said first surface of said each terminal pad overlies said upper surface of said heat sink flange and such that said lower surface of said heat sink flange and said second surface of said each of said terminal pads are in coplanar alignment; electrically connecting said semiconductor die with said first surface of said terminal pads using interconnects; and encasing said flange, said frame structure, said semiconductor die, and said interconnects in an encapsulant wherein at least said lower surface of said heat sink flange and said second surface of said each of said terminal pads remain exposed from said encapsulant. ### Claim 15 (depends on 14) A method as claimed in claim 14 wherein said flange thickness of said heat sink flange is at least thirty mils, and said attaching operation includes using a high temperature die attach process to couple said semiconductor die to said heat sink flange. ### Claim 16 (depends on 14) A method as claimed in claim 14 wherein said each of said terminal pads comprises a folded arrangement having a first section, a second section, and a connector section interconnecting said first and second sections, said first surface being formed on a top side of said first section, said second surface being formed on an underside of said second section, said first section is spaced apart from said upper surface of said heat sink flange by a first gap, said connector section is spaced apart from a lateral sidewall of said heat sink flange by a second gap, and said method further comprises filling said first and second gaps with a dielectric material prior to said encasing operation. ### Claim 17 A packaged leadless semiconductor device comprising: a heat sink flange having an upper surface and a lower surface spaced apart by a flange thickness, said flange thickness being at least thirty mils; a semiconductor die physically coupled to said upper surface of said heat sink flange; a frame structure having a perimeter that defines a cavity and terminal pads surrounding said cavity, each of said terminal pads including a folded arrangement having a first section, a second section, and a connector section interconnecting said first and second sections, wherein a first surface is formed on a top side of said first section, and a second surface is formed on an underside of said second section, said first surface being spaced apart from said second surface by a distance that is at greater than said flange thickness, and said heat sink flange is positioned in said cavity such that said lower surface of said heat sink flange and said second surface of each of said terminal pads are in coplanar alignment, and at least a portion of said first surface of said each of said terminal pads overlies said upper surface of said heat sink flange; interconnects electrically connecting said semiconductor die with said first surface of said terminal pads; and an encapsulant encasing said frame structure, said flange, said semiconductor die, and said interconnects with at least said lower surface of said heat sink flange and said second surface of said each of said terminal pads remaining exposed from said encapsulant. ### Claim 18 (depends on 17) A packaged leadless semiconductor device as claimed in claim 17 wherein said first section is spaced apart from said upper surface of said heat sink flange by a first gap, said connector section is spaced apart from a lateral sidewall of said heat sink flange by a second gap, and said semiconductor device further comprises a dielectric material residing in said first and second gaps. ### Claim 19 (depends on 17) A packaged leadless semiconductor device as claimed in claim 17 wherein said semiconductor die is coupled to said heat sink flange using a high temperature die attach process. ### Claim 20 (depends on 17) A packaged leadless semiconductor device as claimed in claim 17 wherein said connector section has notches formed therein, and said encapsulant is a molding compound encapsulant configured to fill said notches to secure said molding compound encapsulant to said frame structure.