# US 2013/0154066 A1 · Semiconductor package and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154066 A1 - Document ID: US20130154066A1 - Status: Published application - Kind: A1 - Application number: 13/739,565 - Filed: 2013-01-11 - Published: 2013-06-20 - Earliest claimed: 2012-04-12 - Assignees: Amkor Technology, Inc. - Inventors: Dong In Kim; Jae Ung Lee; Eunnara Cho; Min Ju Kim - Web page: https://patentgrep.com/patent/US20130154066A1 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H04R 19/005: {using semiconductor materials} - H04R 19/04: Microphones (H04R19/01 takes precedence) - H10W 90/753: {between laterally-adjacent chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H04R: LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS (producing sounds with frequency not determined by supply frequency G10K) ## Abstract A semiconductor package is presented which has a suitable structure for effectively shielding electromagnetic wave interference (EMI) in a cavity area to which a semiconductor chip is attached. The semiconductor package is assembled such that a lower substrate to which the semiconductor chip is attached is adhered to an EMI shielding & electric I/O body having various types of EMI shielding & electric I/O metal patterns by soldering. Further, the EMI shielding & electric I/O body is adhered to an upper substrate by soldering thereby simplifying assembling of the semiconductor package. ## Claims ### Claim 1 A semiconductor package comprising: a lower substrate; a semiconductor chip coupled to a cavity area of the lower substrate; an electromagnetic wave interference (EMI) shielding & electric input/output (I/O) body formed to surround the cavity area and coupled to the lower substrate by soldering; and an upper substrate coupled to the EMI shielding & electric I/O body by soldering, wherein the EMI shielding & electric I/O body comprises: an EMI shielding & electric I/O hole formed to pass through top and bottom portions of the EMI shielding & electric I/O body; and a first EMI shielding & electric I/O metal pattern coupled to an inner wall of the EMI shielding & electric I/O hole and portions of the top and bottom portions of the EMI shielding & electric I/O body, and comprising a first lower metal pattern coupled to the lower substrate by soldering and a first upper metal pattern coupled to the upper substrate by soldering. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the EMI shielding & electric I/O hole is one of a plurality of EMI shielding & electric I/O holes arranged in constant intervals in the EMI shielding & electric I/O body. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the EMI shielding & electric I/O body further comprises a filler that fills the inside of the EMI shielding & electric I/O hole. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the filler comprises a material selected from the group consisting of a conductive paste and a non-conductive material. ### Claim 5 (depends on 1) The semiconductor package of claim 1 further comprising: a second EMI shielding & electric I/O metal pattern coupled to inner sidewalls facing the cavity area and portions of the top and bottom portions of the EMI shielding & electric I/O body. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the EMI shielding & electric I/O hole is one of a plurality of EMI shielding & electric I/O holes arranged in constant intervals in the EMI shielding & electric I/O body. ### Claim 7 (depends on 5) The semiconductor package of claim 5, wherein the second metal pattern includes a second lower metal pattern coupled to a corresponding surface of the lower substrate, and a second upper metal pattern coupled to a corresponding surface of the upper substrate. ### Claim 8 (depends on 1) The semiconductor package of claim 1 further comprising: a second EMI shielding & electric I/O metal pattern coupled to outer sidewalls back-facing the cavity area and portions of the top and bottom portions of the EMI shielding & electric I/O body. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the second metal pattern comprises a second lower metal pattern coupled to a corresponding surface of the lower substrate, and a second upper metal pattern coupled to a corresponding surface of the upper substrate. ### Claim 10 (depends on 8) The semiconductor package of claim 8, wherein the EMI shielding & electric I/O body further comprises a filler that fills the inside of the EMI shielding & electric I/O hole. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the filler comprises a material selected from the group consisting of a conductive paste and a non-conductive material. ### Claim 12 A semiconductor package comprising: a lower substrate; a semiconductor chip coupled to a cavity area of the lower substrate; an electromagnetic wave interference (EMI) shielding & electric input/output (I/O) body formed to surround the cavity area and coupled to the lower substrate by soldering; and an upper substrate coupled to the EMI shielding & electric I/O body by soldering, wherein the EMI shielding & electric I/O body comprises: a first EMI shielding & electric I/O hole formed to pass through top and bottom portions of the EMI shielding & electric I/O body; a first EMI shielding & electric I/O metal pattern coupled to an inner wall of the EMI shielding & electric I/O hole and portions of the top and bottom portions of the EMI shielding & electric I/O body and comprising a first lower metal pattern coupled to the lower substrate by soldering, and a first upper metal pattern coupled to the upper substrate by soldering; and a second EMI shielding & electric I/O hole; a second EMI shielding & electric I/O metal pattern comprising conductive paste filling the second EMI shielding & electric I/O hole, the second EMI shielding & electric I/O metal pattern further comprising a second lower metal pattern coupled to the lower substrate by soldering and a second upper metal pattern coupled to the upper substrate by soldering. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the first and second EMI shielding & electric I/O holes comprise a plurality of first and second EMI shielding & electric I/O holes arranged in constant intervals in the EMI shielding & electric I/O body. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein the plurality of second EMI shielding & electric I/O holes are arranged to cross the plurality of first EMI shielding & electric I/O holes. ### Claim 15 (depends on 12) The semiconductor package of claim 12, wherein the plurality of second EMI shielding & electric I/O holes are formed at the outside back-facing the cavity area in view of the first EMI shielding & electric I/O holes. ### Claim 16 A semiconductor package comprising: a lower substrate; an electromagnetic wave interference (EMI) shielding & electric input/output (I/O) body comprising: a top surface; a bottom surface; inner sidewalls defining a cavity; a first EMI shielding & electric I/O hole extending through the EMI shielding & electric I/O body from the top surface to the bottom surface; and a first EMI shielding & electric I/O metal pattern at least partially filling the first EMI shielding & electric I/O hole, the first EMI shielding & electric I/O metal pattern comprising: a first lower metal pattern coupled to the bottom surface; and a first upper metal pattern coupled to the top surface; a first lower solder coupling the first lower metal pattern to the lower substrate; an upper substrate; and a first upper solder coupling the first upper metal pattern to the upper substrate. ### Claim 17 (depends on 16) The substrate of claim 16 wherein the EMI shielding & electric I/O body further comprises: a second EMI shielding & electric I/O metal pattern coupled to the inner sidewalls, the second EMI shielding & electric I/O metal pattern comprising: a second lower metal pattern coupled to the bottom surface; and a second upper metal pattern coupled to the top surface; a second lower solder coupling the second lower metal pattern to the lower substrate; and a second upper solder coupling the second upper metal pattern to the upper substrate. ### Claim 18 (depends on 17) The substrate of claim 17 wherein the second EMI shielding & electric I/O metal pattern is coupled to the entire inner sidewalls. ### Claim 19 (depends on 16) The substrate of claim 16 wherein the EMI shielding & electric I/O body further comprises: outer sidewalls facing away from the cavity; a second EMI shielding & electric I/O metal pattern coupled to the outer sidewalls, the second EMI shielding & electric I/O metal pattern comprising: a second lower metal pattern coupled to the bottom surface; and a second upper metal pattern coupled to the top surface; a second lower solder coupling the second lower metal pattern to the lower substrate; and a second upper solder coupling the second upper metal pattern to the upper substrate. ### Claim 20 (depends on 19) The substrate of claim 19 wherein the second EMI shielding & electric I/O metal pattern is coupled to the entire outer sidewalls.