# US 2013/0154057 A1 · Method for Fabricating a DRAM Capacitor

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- Number: US 2013/0154057 A1
- Document ID: US20130154057A1
- Status: Published application
- Kind: A1
- Application number: 13/738,794
- Filed: 2013-01-10
- Published: 2013-06-20
- Earliest claimed: 2011-04-12
- Assignees: Elpida Memory, Inc.; Intermolecular, Inc.
- Inventors: Karthik Ramani; Hanhong Chen; Wim Deweerd; Nobumichi Fuchigami; Hiroyuki Ode
- Web page: https://patentgrep.com/patent/US20130154057A1

## CPC

- H10D 1/68: Capacitors having no potential barriers
- H01G 4/1218: {based on titanium oxides or titanates (H01G4/1245 takes precedence)}
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H10D 1/692: {Electrodes}
- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- Y10T 29/43: Electric condenser making
- Y10T 29/435: Solid dielectric type
- Y10T 29/49002: Electrical device making
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

## Claims

### Claim 1

A semiconductor layer stack comprising:
a first electrode layer formed on a substrate, the first electrode layer comprising a conductive metal oxide;
wherein the first electrode layer has been annealed in a reducing atmosphere;
a dielectric layer formed on the first electrode layer; and
a second electrode layer formed on the dielectric layer.

### Claim 2 (depends on 1)

The semiconductor layer stack of claim 1, wherein the reducing atmosphere comprises one of hydrogen, ammonia, or mixtures thereof.

### Claim 3 (depends on 2)

The semiconductor layer stack of claim 2, wherein the reducing atmosphere is about 1 to 10% hydrogen in nitrogen.

### Claim 4 (depends on 1)

The semiconductor layer stack of claim 1, wherein the annealing is performed at a temperature between about 400 C to about 650 C.

### Claim 5 (depends on 1)

The semiconductor layer stack of claim 1, wherein the annealing is performed using one of thermal energy, plasma energy, or rapid thermal annealing.

### Claim 6 (depends on 1)

The semiconductor layer stack of claim 1 wherein the conductive metal oxide is molybdenum oxide, wherein at least about 40% of the molybdenum oxide is present as crystalline MoO2.

### Claim 7 (depends on 1)

The semiconductor layer stack of claim 1 wherein the dielectric layer is titanium dioxide, wherein at least about 30% of the titanium dioxide is present in the rutile crystalline phase.

### Claim 8 (depends on 1)

The semiconductor layer stack of claim 1, wherein the second electrode layer comprises one of a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, or mixtures thereof.

### Claim 9

A semiconductor layer stack comprising:
a first electrode layer formed on a conductive base layer, wherein the first electrode layer comprises a conductive metal oxide;
wherein the first electrode layer has been annealed in a reducing atmosphere;
a dielectric layer formed on the first electrode layer; and
a second electrode layer formed on the dielectric layer.

### Claim 10 (depends on 9)

The semiconductor layer stack of claim 9, wherein the reducing atmosphere comprises one of hydrogen, ammonia, or mixtures thereof.

### Claim 11 (depends on 10)

The semiconductor layer stack of claim 10, wherein the reducing atmosphere is about 1 to 10% hydrogen in nitrogen.

### Claim 12 (depends on 9)

The semiconductor layer stack of claim 9, wherein the annealing is performed at a temperature between about 400 C to about 650 C.

### Claim 13 (depends on 9)

The semiconductor layer stack of claim 9, wherein the annealing is performed using one of thermal energy, plasma energy, or rapid thermal annealing.

### Claim 14 (depends on 9)

The semiconductor layer stack of claim 9 wherein the conductive metal oxide is molybdenum oxide, wherein at least about 40% of the molybdenum oxide is present as crystalline MoO2

### Claim 15 (depends on 9)

The semiconductor layer stack of claim 9 wherein the dielectric layer is titanium dioxide, wherein at least about 30% of the titanium dioxide is present in the rutile crystalline phase

### Claim 16 (depends on 9)

The semiconductor layer stack of claim 9, wherein the second electrode comprises a layer of at least one of a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, or mixtures thereof.