# US 2013/0154053 A1 · Inductors with through vias

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0154053 A1
- Document ID: US20130154053A1
- Status: Published application
- Kind: A1
- Application number: 13/330,127
- Filed: 2011-12-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsiao-Tsung Yen; Yu-Ling Lin
- Web page: https://patentgrep.com/patent/US20130154053A1

## CPC

- H01F 17/0006: {Printed inductances (printed coils for dynamo-electric machines H02K3/26; printed circuits H05K)}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H01F 2017/002: {Details of via holes for interconnecting the layers}
- H01F 2017/0053: {with means to reduce eddy currents}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate.

## Claims

### Claim 1

An apparatus comprising:
a substrate;
one or more dielectric layers overlying the substrate;
one or more dummy vias extending through one or more of the one or more dielectric layers; and
an inductor overlying the one or more vias.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the one or more vias extend into the substrate.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the one or more vias extend through the substrate.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the one or more vias are not electrically coupled to the inductor.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the one or more vias are positioned directly below the inductor.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein a diameter of the one or more vias is equal to or greater than a width of a trace of the inductor.

### Claim 7

An apparatus comprising:
a substrate having a plurality of overlying dielectric layers;
at least one through via extending into the substrate; and
an inductor formed in one or more of the dielectric layers, at least a portion of the inductor directly overlying the at least one through via.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the at least one through via comprises a dielectric liner and a conductive fill material.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the liner has a thickness from about 0.1 μm to about 1.5 μm.

### Claim 10 (depends on 7)

The apparatus of claim 7, wherein the at least one through via extends completely through the substrate.

### Claim 11 (depends on 7)

The apparatus of claim 7, wherein the inductor and the at least one through via is separated by one of more dielectric layers.

### Claim 12 (depends on 7)

The apparatus of claim 7, further comprising one or more through vias not directly underlying the inductor, the one or more through vias not directly underlying the inductor being electrically isolated.

### Claim 13 (depends on 7)

The apparatus of claim 7, wherein the at least one through via is filled with a dielectric material.

### Claim 14

A method of forming an electrical device:
providing a substrate;
forming one or more first dielectric layers over the substrate;
forming one or more through vias through at least one of the one or more first dielectric layers;
forming one or more second dielectric layers over the through vias; and
forming an inductor in one or more of the one or more second dielectric layers, the inductor directly overlying at least some of the through vias.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the one or more through vias comprises:
forming holes through the one or more first dielectric layers;
forming a dielectric liner along surfaces of the holes; and
forming a conductive material over the dielectric liner.

### Claim 16 (depends on 14)

The method of claim 14, wherein a diameter of the one or more vias is equal to or greater than a width of a trace of the inductor.

### Claim 17 (depends on 14)

The method of claim 14, wherein a diameter of the one or more vias is greater than twice a width of a trace of the inductor.

### Claim 18 (depends on 14)

The method of claim 14, wherein the forming the one or more through vias comprises forming one or more through vias extending into the substrate.

### Claim 19 (depends on 18)

The method of claim 18, further comprising thinning a backside of the substrate, thereby exposing the one or more through vias.

### Claim 20 (depends on 14)

The method of claim 14, wherein the through vias are filled with a dielectric material.