# US 2013/0154029 A1 · Embedded stressors for multigate transistor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154029 A1 - Document ID: US20130154029A1 - Status: Published application - Kind: A1 - Application number: 13/611,068 - Filed: 2012-09-12 - Published: 2013-06-20 - Earliest claimed: 2011-12-14 - Assignees: International Business Machines Corporation - Inventors: Ming Cai; Dechao Guo; Pranita Kulkarni; Chun-Chen Yeh - Web page: https://patentgrep.com/patent/US20130154029A1 ## CPC - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region. ## Claims ### Claim 1 A multigate transistor device comprising: a gate structure including a gate electrode and a gate dielectric; a channel region that includes a plurality of surfaces on which the gate structure is disposed and is configured to provide the conductive channel for charge carriers between a source and a drain of the device in response to activation by the gate structure; a recessed portion that is under the gate structure and under the conductive channel and includes at least one angled indentation; and source and drain extensions that are in contact with the conductive channel, wherein at least one of the source or drain extensions extends into the at least one angled indentation under the conductive channel and provides a stress on the conductive channel such that charge carrier mobility is enhanced in the channel region. ### Claim 2 (depends on 1) The multigate transistor device of claim 1, wherein the recessed portion and the channel region form a cohesive lattice structure and wherein the at least one of the source or drain extensions has a lattice structure that is different from the lattice structure of the channel region and the recessed portion. ### Claim 3 (depends on 1) The multigate transistor device of claim 1, wherein the at least one angled indentation is sigma-shaped. ### Claim 4 (depends on 1) The multigate transistor device of claim 1, wherein the at least one angled indentation commences from a bottom of the channel region. ### Claim 5 (depends on 1) The multigate transistor device of claim 1, further comprising: a base portion that is below the recessed portion and extends from below the channel region to below the at least one of the source or drain extensions. ### Claim 6 (depends on 5) The multigate transistor device of claim 5, wherein the channel region, the recessed portion and the base portion form a cohesive lattice structure and wherein the at least one of the source or drain extensions has a lattice structure that is different from the lattice structure of the channel region, the recessed portion and the base portion. ### Claim 7 A circuit apparatus comprising: a plurality of multigate devices and a gate structure, wherein each of the multigate devices includes a channel region, a recessed portion and a terminal extension, wherein the channel region includes a plurality of surfaces on which the gate structure is disposed and is configured to provide the conductive channel for charge carriers between a source and a drain of the respective multigate device in response to activation by the gate structure, wherein the recessed portion is under the gate structure and under the conductive channel and includes at least one angled indentation, and wherein the terminal extensions of the multigate devices form a cohesive lattice structure that is in contact with each of the conductive channels of the multigate devices, extends into each of the indentations under the conductive channels of the multigate devices and provides stresses on the conductive channels such that charge carrier mobility is enhanced in the channel regions. ### Claim 8 (depends on 7) The circuit apparatus of claim 7, wherein the recessed portion and the channel region of each of the multigate devices form a respective cohesive lattice structure that is different from the lattice structure of the terminal extensions. ### Claim 9 (depends on 7) The circuit apparatus of claim 7, wherein the at least one angled indentation of at least one of the multigate devices is sigma-shaped. ### Claim 10 (depends on 7) The circuit apparatus of claim 7, wherein the at least one angled indentation of at least one of the multigate devices commences from a bottom of the respective channel region. ### Claim 11 (depends on 7) The circuit apparatus of claim 7, wherein at least one of the multigate devices further comprises a base portion that is below the respective recessed portion and that extends from below the respective channel region to below the respective terminal extension. ### Claim 12 (depends on 11) The circuit apparatus of claim 11, wherein the respective channel region, the respective recessed portion and the base portion form a cohesive lattice structure that is different from the lattice structure of the terminal extensions. ### Claim 13 (depends on 1) The multigate transistor device of claim 1, wherein the at least one angled indentation is disposed under the gate electrode. ### Claim 14 (depends on 7) The circuit apparatus of claim 7, wherein the at least one angled indentation of each respective multigate device is disposed under a gate electrode of the gate structure of the respective multigate device.