# US 2013/0154028 A1 · Fin-type field effect transistor

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- Number: US 2013/0154028 A1
- Document ID: US20130154028A1
- Status: Published application
- Kind: A1
- Application number: 13/326,429
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: United Microelectronics Corp.
- Inventors: Chih-Jung WANG; Tong-Yu CHEN
- Web page: https://patentgrep.com/patent/US20130154028A1

## CPC

- H10D 86/215: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

## Claims

### Claim 1

A fin-type field effect transistor, comprising:
at least one fin-type semiconductor structure doped with a first type dopant, the at least one fin-type semiconductor structure has a channel region and a blocking region, the blocking region has a first doping concentration, the channel region has a second doping concentration smaller than the first doping concentration, the blocking region has a height and the channel region defined above the blocking region;
a gate strip, substantially parallel to the at least one fin-type semiconductor structure and covers on the channel region; and
a gate insulating layer, disposed between the gate strip and the at least one fin-type semiconductor structure.

### Claim 2 (depends on 1)

The fin-type field effect transistor recited in claim 1, further comprises a source structure and a drain structure doped with a second type dopant, wherein the fin-type semiconductor .structure is connected between the source structure and the drain structure.

### Claim 3 (depends on 1)

The fin-type field effect transistor recited in claim 1, wherein the gate strip conformally covers a portion of the at least one fin-type semiconductor structure.

### Claim 4 (depends on 1)

The fin-type field effect transistor recited in claim 1, wherein material of the gate strip comprises polysilicon.

### Claim 5 (depends on 1)

The fin-type field effect transistor recited in claim 1, comprising a plurality of the fin-type semiconductor structures parallel to each other, the fin-type semiconductor structures have the same height and the blocking regions of the fin-type semiconductor structures have different heights.

### Claim 6 (depends on 1)

The fin-type field effect transistor recited in claim 1, further comprises a semiconductor substrate with a plurality of trenches substantially parallel to each other, wherein the at least one fin-type semiconductor structure is defined between the adjacent trenche.

### Claim 7 (depends on 1)

The fin-type field effect transistor recited in claim 1, wherein the gate strip is evenly configured on the semiconductor substrate and, the trenches being filled therewith and the channel region being covered.

### Claim 8 (depends on 6)

The fin-type field effect transistor recited in claim 6, further comprises a plurality of insulating structures configured within the trenches and the gate strip configured thereon, wherein the top surface of the blocking region is higher than the top surface of each insulating structure.

### Claim 9 (depends on 6)

The fin-type field effect transistor recited in claim 6, wherein material of the gate strip comprises metal and material of the gate insulating layer comprises high-K materials.

### Claim 10 (depends on 1)

The fin-type field effect transistor recited in claim 1, further comprising an insulating layer configured on a top surface of the gate insulating layer and between the gate strip and the gate insulating layer.