# US 2013/0154024 A1 · Structure and method of latchup robustness with placement of through wafer via within cmos circuitry

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- Number: US 2013/0154024 A1
- Document ID: US20130154024A1
- Status: Published application
- Kind: A1
- Application number: 13/768,050
- Filed: 2013-02-15
- Published: 2013-06-20
- Earliest claimed: 2008-08-06
- Assignees: International Business Machines Corporation
- Inventors: Phillip F. CHAPMAN; David S. COLLINS; Steven H. VOLDMAN
- Web page: https://patentgrep.com/patent/US20130154024A1

## CPC

- H10D 84/854: {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

## Claims

### Claim 1

A semiconductor structure, comprising:
an NFET device having a P-well at a top side of a substrate;
a PFET device having an N-well at the top side of the substrate; and
a substrate contact comprising a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure located between the NFET device and the PFET device,
wherein the substrate contact is arranged to prevent formation of a parasitic circuit.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the through wafer via is in contact with and at substantially a same electrical potential as one of the P-well and the N-well, and is remote from the other of the P-well and the N-well, respectively.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein a top portion of the through wafer via contacts a bottom portion of the isolation structure.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the isolation structure comprises one of:
a shallow trench isolation (STI) structure,
a trench isolation (TI) structure formed through a shallow trench isolation (STI) structure, and
a deep trench (DT) structure formed below a shallow trench isolation (STI) structure.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, further comprising a dopant out-diffused from surfaces of a via opening of the through wafer via into the substrate and a deep well.

### Claim 6

A semiconductor structure, comprising:
an NFET device having a P-well at a top side of a substrate;
a PFET device having an N-well at the top side of the substrate;
a deep well formed in the substrate below the N-well and the P-well;
a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure;
an electrical connection region between the through wafer via and the deep well; and
a high voltage junction between the through wafer via and the substrate.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein a top portion of the through wafer via contacts a bottom portion of the isolation structure.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the isolation structure comprises one of:
a shallow trench isolation (STI) structure,
a trench isolation (TI) structure formed through a shallow trench isolation (STI) structure, and
a deep trench (DT) structure formed below a shallow trench isolation (STI) structure.

### Claim 9 (depends on 6)

The semiconductor structure of claim 6, wherein the through wafer via contacts the bottom surface of the isolation structure.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the electrical connection region and the high voltage junction comprise a dopant out-diffused from surfaces of a via opening of the through wafer via.