# US 2013/0154020 A1 · System, method and apparatus for seedless electroplated structure on a semiconductor substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154020 A1 - Document ID: US20130154020A1 - Status: Published application - Kind: A1 - Application number: 13/328,218 - Filed: 2011-12-16 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: Hitachi Global Storage Technologies Netherlands B.V. - Inventors: Christian René Bonhôte; Jeffrey S. Lille; Ricardo Ruiz; Georges Gibran Siddiqi - Web page: https://patentgrep.com/patent/US20130154020A1 ## CPC - H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation} - H10D 30/0212: {using self-aligned silicidation} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0172: {Manufacturing their gate conductors} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit has a doped silicon semiconductor with regions of insulators and bare silicon. The bare silicon regions are isolated from other bare silicon regions. A semiconductor device on the doped silicon semiconductor has at least two electrical connections to form regions of patterned metal. A metal is electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer. A self-aligned silicide is located under each plated connection, formed by annealing, for the regions of plated metal on bare silicon. ## Claims ### Claim 1 An integrated circuit (IC), comprising: a doped silicon semiconductor having regions of insulators and regions of bare silicon, and the bare silicon regions are isolated from other bare silicon regions; a semiconductor device on the doped silicon semiconductor, the semiconductor device having at least two electrical connections to form regions of patterned metal; a metal electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer; and a self-aligned silicide under each plated connection. ### Claim 2 (depends on 1) An IC according to claim 1, wherein said at least two electrical connections comprise at least one of a source, a drain, and a gate connection. ### Claim 3 (depends on 1) An IC according to claim 1, wherein the IC is a complementary metal-oxide semiconductor (CMOS). ### Claim 4 (depends on 1) An IC according to claim 1, wherein the electroplated metal comprises Ni, Co, Ta, Ti, Mo or combinations thereof. ### Claim 5 (depends on 1) An IC according to claim 1, wherein the self-aligned silicide comprises NiSix, CoSix, TaSix, TiSix, MoSix or combinations thereof, and the self-aligned silicide is formed by annealing. ### Claim 6 (depends on 1) An IC according to claim 1, wherein the semiconductor device comprises a plurality of semiconductor devices on a phase change memory or flash memory. ### Claim 7 A method of forming a seedless electroplated metal on a semiconductor surface, comprising: providing a silicon substrate; forming a mask directly on the silicon substrate without a seed layer, the mask having a thickness of less than 100 nm, and the mask having openings with widths that are less than 100 nm; wherein the substrate is masked in regions of insulators and regions of silicon, and the silicon regions are isolated from other silicon regions; coating the substrate with a polymer that is compatible with a block copolymer (BCP) to allow the BCP to produce a desired mask pattern, the BCP chemically bonds to the substrate at locations of the silicon regions, the polymer having equal chemical affinity to different constituents of the BCP, and the BCP forming the desired mask pattern via phase separation, and the desired mask pattern has part of the BCP removed to expose the substrate; removing an oxide on the silicon substrate with buffered oxide etch (BOE) containing a surfactant; and electroplating a metal through the mask to form electrical connections on the silicon substrate, and the silicon substrate acts as a cathode to form plated electrical connections. ### Claim 8 (depends on 7) A method according to claim 7, wherein the mask thickness is 50 nm or less ### Claim 9 (depends on 7) A method according to claim 7, wherein the electrical connections comprise metal wires or vias. ### Claim 10 (depends on 7) A method according to claim 7, wherein the BCP forms the desired mask pattern via phase separation into either lamella or a hexagonally closed packed arrangement. ### Claim 11 (depends on 7) A method according to claim 7, wherein the BCP comprises a tri-block copolymer. ### Claim 12 (depends on 7) A method according to claim 7, wherein the BCP comprises a silicon-containing polymer. ### Claim 13 (depends on 7) A method according to claim 7, wherein the BCP comprises layers of poly(styrene-random-methyl methacrylate) (PS-r-PMMA) and poly(styrene-block-methyl methacrylate) (PS -b-PMMA). ### Claim 14 (depends on 7) A method according to claim 7, further comprising coating the substrate with a chemically-neutral polymer, and removing the chemically-neutral polymer by etching with an oxygen-containing plasma. ### Claim 15 (depends on 7) A method according to claim 7, wherein removing the oxide comprises about 1 minute to about 15 minutes in BOE containing the surfactant. ### Claim 16 (depends on 7) A method according to claim 7, further comprising additional mask and etching steps to break the plated electrical connections formed by electroplating the metal. ### Claim 17 (depends on 7) A method according to claim 7, further comprising annealing to form a self-aligned silicide with the plated electrical connections. ### Claim 18 An integrated circuit (IC), comprising: a doped silicon semiconductor having regions of insulators and regions of bare silicon, the bare silicon regions are isolated from other bare silicon regions; a semiconductor device on the doped silicon semiconductor, the semiconductor device having at least two electrical connections to form regions of patterned metal, said at least two electrical connections comprise at least one of a source, a drain, and a gate connection; a metal electroplated directly on each of the regions of patterned metal to form plated connections without a seed layer; and a self-aligned silicide under each plated connection, formed by annealing, for the regions of plated metal on bare silicon. ### Claim 19 (depends on 18) An IC according to claim 18, wherein the IC is a complementary metal-oxide semiconductor (CMOS). ### Claim 20 (depends on 18) An IC according to claim 18, wherein the electroplated metal comprises Ni, Co, Ta, Ti, Mo or combinations thereof. ### Claim 21 (depends on 18) An IC according to claim 18, wherein the self-aligned silicide comprises NiSix, CoSix, TaSix, TiSix, MoSix or combinations thereof. ### Claim 22 (depends on 18) An IC according to claim 18, wherein the semiconductor device comprises a plurality of semiconductor devices on a phase change memory or flash memory. ### Claim 23 (depends on 18) An IC according to claim 18, wherein the electrical connections comprise metal wires or vias. ### Claim 24 (depends on 18) An IC according to claim 18, further comprising a coating on the substrate with a chemically-neutral polymer, and the chemically-neutral polymer is removed by etching with an oxygen-containing plasma. ### Claim 25 (depends on 18) An IC according to claim 18, further comprising mask and etch to break the plated connections formed by electroplating the metal.