# US 2013/0154019 A1 · Low threshold voltage cmos device

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- Number: US 2013/0154019 A1
- Document ID: US20130154019A1
- Status: Published application
- Kind: A1
- Application number: 13/327,870
- Filed: 2011-12-16
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: International Business Machines Corporation
- Inventors: Takashi Ando; Changhwan Choi; Kisik Choi; Vijay Narayanan
- Web page: https://patentgrep.com/patent/US20130154019A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/0135: {by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.

## Claims

### Claim 1

A semiconductor device comprising:
an NMOS region and a PMOS region;
the NMOS region having a gate structure comprising a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material;
the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material;
wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein the first high-k gate dielectric constant includes lanthanum.

### Claim 3 (depends on 2)

The semiconductor device of claim 2 wherein the first high-k gate dielectric and lanthanum are in separate layers with the lanthanum underneath the first high-k gate dielectric.

### Claim 4 (depends on 1)

The semiconductor device of claim 1 wherein the second high-k gate dielectric includes aluminum.

### Claim 5 (depends on 4)

The semiconductor device of claim 4 wherein the second high-k gate dielectric and aluminum are in separate layers with the aluminum underneath the second high-k gate dielectric.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 wherein the first high-k gate dielectric includes lanthanum and wherein the second high-k gate dielectric includes aluminum.

### Claim 7 (depends on 1)

The semiconductor device of claim 1 wherein the first work function setting metal comprises aluminum, titanium aluminum, titanium aluminum nitride, tantalum aluminum, tantalum aluminum nitride, hafnium silicon alloy, hafnium nitride, or tantalum carbide, and the second work function setting metal comprises titanium nitride, tungsten, tantalum nitride, ruthenium, platinum, rhenium, iridium, or palladium.

### Claim 8 (depends on 1)

The semiconductor device of claim 1 wherein the first work function setting metal sets the work function at the silicon conduction band edge and the second work function setting metal sets the work function at the silicon valence band edge.

### Claim 9 (depends on 1)

The semiconductor device of claim 1 wherein the PMOS region further including a layer of silicon germanium underneath the second high-k gate dielectric.

### Claim 10

A method of making a semiconductor device comprising:
providing a substrate having an NMOS region and a PMOS region;
forming a high-k dielectric layer over the NMOS region and the PMOS region;
incorporating a metal into the high-k dielectric layer over at least one of the NMOS region and the PMOS region wherein the metal is lanthanum if incorporated into the high-k dielectric over the NMOS region and the metal is aluminum if incorporated into the high-k dielectric over the PMOS region;
depositing a nitride or carbide layer over the NMOS and PMOS regions;
depositing a silicon layer over the nitride layer;
patterning a gate structure of the nitride layer and the silicon layer over the NMOS and PMOS regions;
applying an interlevel dielectric between the gate structure over the NMOS region and the gate structure over the PMOS region;
removing the silicon layer from the gate structure over the NMOS region and the gate structure over the PMOS region to leave an opening in the gate structures;
depositing a first work function setting metal in the opening over the NMOS region and depositing a second work function setting metal in the opening over the PMOS region to partially fill the openings; and
depositing a fill metal to fill the openings.

### Claim 11 (depends on 10)

The method of claim 10 wherein the first high-k gate dielectric includes lanthanum.

### Claim 12 (depends on 10)

The method of claim 10 wherein the second high-k gate dielectric includes aluminum.

### Claim 13 (depends on 10)

The method of claim 10 wherein the first high-k gate dielectric includes lanthanum and wherein the second high-k gate dielectric includes aluminum.

### Claim 14 (depends on 10)

The method of claim 10 wherein the first work function setting metal comprises aluminum or titanium aluminum and the second work function setting metal comprises titanium nitride.

### Claim 15 (depends on 10)

The method of claim 10 wherein the first work function setting metal sets the work function at the silicon conduction band edge and the second work function setting metal sets the work function at the silicon valence band edge.

### Claim 16 (depends on 10)

The method of claim 10 wherein the PMOS region further includes a layer of silicon germanium underneath the high-k gate dielectric.

### Claim 17

A method of making a semiconductor device comprising:
providing a substrate having an NMOS region and a PMOS region;
forming a gate structure on each of the NMOS region and the PMOS region;
applying an interlevel dielectric between the gate structure over the NMOS region and the gate structure over the PMOS region;
removing the gate structure over the NMOS region and the gate structure over the PMOS region to leave an opening in the interlevel dielectric over each of the NMOS region and the PMOS region;
depositing at least one of: lanthanum oxide in the opening over the NMOS region, aluminum oxide in the opening over the PMOS region;
depositing a high-k dielectric in each of the openings over the NMOS region and the PMOS region;
depositing a first work function setting metal in the opening over the NMOS region and depositing a second work function setting metal in the opening over the PMOS region to partially fill the openings; and
depositing a fill metal to fill the openings.

### Claim 18 (depends on 17)

The method of claim 17 wherein lanthanum is deposited in the opening over the NMOS region.

### Claim 19 (depends on 17)

The method of claim 17 wherein aluminum is deposited in the opening over the PMOS region.

### Claim 20 (depends on 17)

The method of claim 17 wherein lanthanum is deposited in the opening over the NMOS region and wherein aluminum is deposited in the opening over the PMOS region.

### Claim 21 (depends on 17)

The method of claim 17 wherein the first work function setting metal comprises aluminum, titanium aluminum, titanium aluminum nitride, tantalum aluminum, tantalum aluminum nitride, hafnium silicon alloy, hafnium nitride, or tantalum carbide, and the second work function setting metal comprises titanium nitride, tungsten, tantalum nitride, ruthenium, platinum, rhenium, iridium, or palladium.

### Claim 22 (depends on 17)

The method of claim 17 wherein the first work function setting metal sets the work function at the silicon conduction band edge and the second work function setting metal sets the work function at the silicon valence band edge.

### Claim 23 (depends on 17)

The method of claim 17 wherein the PMOS region further includes a layer of silicon germanium.