# US 2013/0154017 A1 · Self-Aligned Gate Structure for Field Effect Transistor

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- Number: US 2013/0154017 A1
- Document ID: US20130154017A1
- Status: Published application
- Kind: A1
- Application number: 13/709,342
- Filed: 2012-12-10
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Microchip Technology Incorporated
- Inventors: Gregory Dix; Harold Kline; Rodney Schroeder; Daniel J. Grimm
- Web page: https://patentgrep.com/patent/US20130154017A1

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 64/0133: {at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A field effect transistor has a substrate with an epitaxial layer, base regions extending from a top of the epitaxial layer into the epitaxial layer, an insulation region having side walls and extending between two base regions on top of the substrate; and a polysilicon gate structure covering the insulation region including the side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above the base region.

## Claims

### Claim 1

A method for manufacturing a field effect transistor comprising:
providing a stack comprising a substrate and epitaxial layer deposited on said substrate, a multilayer insulating layer on top of the epitaxial layer, and a first gate-layer on top of the insulating layer;
patterning the stack to provide openings up to a lowest layer of the multi-layer insulating layer;
implanting base regions;
depositing a second gate layer covering the openings and the first gate layer;
performing an etching up to the lowest layer of the multi-layer insulating layer such that spacers on sides of the openings remain and form respective gate structures of the field effect transistor.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the multi-layer insulating layer comprises a first oxide layer on top of the substrate, a nitride layer on top of the first oxide layer; a second oxide layer on top of the nitride layer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the first layer is a Gate oxide.

### Claim 4 (depends on 1)

The method according to claim 1, wherein each layer of the multi-layer insulating layer has a different thickness.

### Claim 5 (depends on 2)

The method according to claim 2, wherein the Gate oxide layer has a thickness of approximately 250 Å, the nitride layer of approximately 400 Å, the thick oxide layer of approximately 2500 Å, and the first polysilicon layer of approximately 1500 Å.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the second polysilicon layer has a thickness of approximately 2500 Å.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the two adjacent gate structures in adjacent openings are bridged by said first polysilicon layer.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising the step of forming self-aligned source regions within the base regions.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the thickness of the multi-layer insulating layer is chosen such that a capacitance between the first polysilicon layer and a drain region is minimized.

### Claim 10

A field effect transistor comprising:
a substrate comprising an epitaxial layer;
Base regions extending from a top of the epitaxial layer into the epitaxial layer;
an insulation region having side walls and extending between two base regions on top of the substrate;
a polysilicon gate structure covering said insulation region including said side walls, wherein effective gates are formed by a portion of the polysilicon covering side walls above said base region.

### Claim 11 (depends on 10)

The field effect transistor according to claim 10, wherein the insulation region comprises a multi-layer insulating structure comprising: a first oxide layer on top of the epitaxial layer, a nitride layer on top of the first oxide layer, a second oxide layer on top of the nitride layer.

### Claim 12 (depends on 10)

The field effect transistor according to claim 10, wherein the polysilicon gate structure comprises a first and a second polysilicon layer, wherein the first polysilicon layer covers the insulation region and the second layer includes spacers covering said side walls and forming said effective gates.

### Claim 13 (depends on 11)

The field effect transistor according to claim 11, wherein the first layer is a Gate oxide.

### Claim 14 (depends on 11)

The field effect transistor according to claim 11, wherein each layer of the multi-layer insulation structure has a different thickness.

### Claim 15 (depends on 13)

The field effect transistor according to claim 13, wherein the Gate oxide layer has a thickness of approximately 250 Å, the nitride layer of approximately 400 Å, the thick oxide layer of approximately 2500 Å, and the first polysilicon layer of approximately 1500 Å.

### Claim 16 (depends on 12)

The field effect transistor according to claim 12, wherein the second polysilicon layer has a thickness of approximately 2500 Å.

### Claim 17 (depends on 10)

The field effect transistor according to claim 10, wherein the two adjacent gate structures in adjacent openings are bridged by a polysilicon layer.

### Claim 18 (depends on 10)

The field effect transistor according to claim 10, further comprising self-aligned source regions within the base regions.

### Claim 19 (depends on 12)

The field effect transistor according to claim 12, wherein the thickness of the multi-layer insulation structure is chosen such that a capacitance between the first polysilicon layer and a drain region is minimized.

### Claim 20 (depends on 10)

The field effect transistor according to claim 10, wherein a drain region is formed under said insulation region.