# US 2013/0154016 A1 · Tin doped iii-v material contacts

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- Number: US 2013/0154016 A1
- Document ID: US20130154016A1
- Status: Published application
- Kind: A1
- Application number: 13/685,369
- Filed: 2012-11-26
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Intel Corporation
- Inventors: Glenn A. Glass; Anand S. Murthy; Michael J. Jackson; Harold W. Kennel
- Web page: https://patentgrep.com/patent/US20130154016A1

## CPC

- H10D 62/82: Heterojunctions
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/854: further characterised by the dopants
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/418: {the conductive layers comprising transition metals}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.

## Claims

### Claim 1

A semiconductor integrated circuit, comprising:
a substrate having a channel region;
a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region;
source and drain regions in the substrate and adjacent to the channel region;
a tin doped III-V material layer on at least a portion of the source and drain regions; and
source and drain metal contacts on the III-V material layer.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 wherein at least a portion of the tin doped III-V material layer is oxidized.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 wherein a portion of the tin doped III-V material layer is oxidized, such that the source and drain metal contacts are in contact with the oxidized portion of the tin doped III-V material layer.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 wherein substantially all of the tin doped III-V material layer is oxidized.

### Claim 5 (depends on 1)

The integrated circuit of claim 1 wherein the tin doped III-V material layer has a graded tin concentration.

### Claim 6 (depends on 5)

The integrated circuit of claim 5 wherein the tin doped III-V material layer has a tin concentration that is higher near the source and drain metal contacts than the tin concentration near the substrate.

### Claim 7 (depends on 5)

The integrated circuit of claim 5 wherein the tin doped III-V material layer has a semiconducting phase and an oxide phase.

### Claim 8 (depends on 1)

The integrated circuit of claim 1 wherein the tin doped III-V material layer has a semiconducting phase and an oxide phase.

### Claim 9 (depends on 8)

The integrated circuit of claim 8 wherein the tin doped III-V material layer has a tin concentration in the range of 0.003% to 1.0% in the semiconducting phase and in the range of 2.5% to 20% in the oxide phase.

### Claim 10 (depends on 1)

The integrated circuit of claim 1 wherein the integrated circuit is implemented with a planar transistor architecture.

### Claim 11 (depends on 1)

The integrated circuit of claim 1 wherein the integrated circuit is implemented with a non-planar transistor architecture.

### Claim 12 (depends on 11)

The integrated circuit of claim 11 wherein the non-planar transistor architecture comprises at least one of a fin-based transistor and/or a nanowire transistor.

### Claim 13 (depends on 1)

The integrated circuit of claim 1 wherein the source/drain regions are n-type and comprise silicon or germanium or an alloy thereof, or a III-V material.

### Claim 14 (depends on 1)

An electronic device comprising:
a printed circuit board having one or more integrated circuits as defined in claim 1.

### Claim 15 (depends on 14)

The electronic device of claim 14 wherein the one or more integrated circuits comprise at least one of a communication chip and/or a processor.

### Claim 16 (depends on 14)

The electronic device of claim 14 wherein the device is a mobile computing device.

### Claim 17

A device, comprising:
a silicon-containing substrate having a number of channel regions;
a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region;
n-type source/drain regions in the substrate and adjacent to a corresponding channel region, the n-type source/drain regions comprising silicon or germanium or an alloy thereof, or a III-V material;
a tin doped III-V material layer on at least a portion of the n-type source drain regions; and
a metal contact on the tin doped III-V material layer for each of the n-type source/drain regions.

### Claim 18 (depends on 17)

The device of claim 17 wherein at least a portion of the tin doped III-V material layer is oxidized.

### Claim 19 (depends on 18)

The device of claim 18 wherein the source and drain metal contacts are in contact with an oxidized portion of the tin doped III-V material layer.

### Claim 20 (depends on 17)

The device of claim 17 wherein substantially all of the tin doped III-V material layer is oxidized.

### Claim 21 (depends on 17)

The device of claim 17 wherein the tin doped III-V material layer has a tin concentration that is higher near the source and drain metal contacts than the tin concentration near the substrate.

### Claim 22 (depends on 17)

The device of claim 17 wherein the tin doped III-V material layer has a semiconducting phase and an oxide phase.

### Claim 23 (depends on 22)

The device of claim 22 wherein the semiconducting phase has a tin concentration in the range of 0.003% to 1.0% and the oxide phase has a tin concentration in the range of 2.5% to 20%.

### Claim 24

A method for forming a semiconductor device, comprising:
providing a substrate having a channel region;
providing a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region;
providing source/drain regions in the substrate and adjacent to the channel region;
providing a tin doped III-V material layer on at least a portion of the source/drain regions; and
providing a metal contact on the tin doped III-V material layer.

### Claim 25 (depends on 24)

The method of claim 24 wherein the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact, and the semiconducting phase has a tin concentration in the range of 0.003% to 1.0% and the oxide phase has a tin concentration in the range of 2.5% to 20%.