# US 2013/0154014 A1 · Semiconductor Device and Method for Fabricating the Same

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- Number: US 2013/0154014 A1
- Document ID: US20130154014A1
- Status: Published application
- Kind: A1
- Application number: 13/424,148
- Filed: 2012-03-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: Dongbu HiTek Co., Ltd.
- Inventors: Soonyeol PARK
- Web page: https://patentgrep.com/patent/US20130154014A1

## CPC

- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming an shallow trench isolation (STI) in a substrate, sequentially forming an oxide layer and a nitride layer over the substrate, patterning the nitride layer and the oxide layer to expose a portion of the substrate adjacent to the STI layer, forming a field oxide layer contacting the STI layer in the exposed portion of the substrate, removing the nitride layer, etching a portion of the patterned oxide layer to form a first gate oxide layer contacting the field oxide layer, forming a second gate oxide layer over the substrate, and forming a gate pattern over the field oxide layer, the first gate oxide layer, and the second gate oxide layer.

## Claims

### Claim 1

A method for fabricating a semiconductor device, the method comprising:
etching a portion of a semiconductor substrate to form a shallow trench isolation (STI) layer;
sequentially forming an oxide layer and a nitride layer on or over the semiconductor substrate and the STI layer;
patterning the nitride layer and the oxide layer to expose a portion of the semiconductor substrate adjacent to the STI layer and to define a field oxide region;
forming a field oxide layer in contact with the STI layer in the exposed portion of the semiconductor substrate;
removing the nitride layer;
etching the patterned oxide layer to form a first gate oxide layer in contact with the field oxide layer;
forming a second gate, oxide layer on the semiconductor substrate; and
forming a gate pattern on or over the field oxide layer, the first gate oxide layer, and the second gate oxide layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first gate oxide layer is thicker than the second gate oxide layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first gate oxide layer is in contact with an end portion of the field oxide.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the first gate oxide layer comprises:
forming a photoresist pattern covering a portion of the patterned oxide layer in contact with the field oxide layer;
forming the first gate oxide layer by removing areas of the oxide layer exposed by the photoresist pattern; and
removing the photoresist pattern.

### Claim 5 (depends on 1)

The method of claim 1, wherein the field oxide layer has an edge portion that is in contact with an upper edge of the STI layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gate pattern covers an entire width of the field oxide layer, the entire first gate oxide layer, and the entire second gate oxide layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the gate pattern is on or over a portion of the STI layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the STI layer has a depth less than 150 nm.

### Claim 9

A semiconductor device, comprising:
a shallow trench isolation (STI) layer in a semiconductor substrate;
a field oxide layer in a portion of the semiconductor substrate adjacent to the STI layer;
a first gate oxide layer on or over the semiconductor substrate and adjacent to the field oxide layer;
a second gate oxide layer on or over the semiconductor substrate at sides of the first gate oxide layer; and
a gate pattern on or over the field oxide layer, the first gate oxide layer, and the second gate oxide layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first gate oxide layer is thicker than the second gate oxide layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first gate oxide layer is in contact with an edge portion of the field oxide layer.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein an edge portion of the field oxide layer is in contact with an upper edge of the STI layer.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the gate pattern covers an entire width of the field oxide layer, the entire first gate oxide layer, and the entire second gate oxide layer.

### Claim 14 (depends on 9)

The method of claim 9, wherein the STI layer has a depth less than 150 nm.

### Claim 15

A method for fabricating a semiconductor device, comprising:
forming a shallow trench isolation (STI) layer in a substrate;
forming a field oxide layer adjacent to the STI layer in the semiconductor substrate;
forming a first gate oxide layer adjacent to the field oxide layer;
forming a second gate oxide layer adjacent to the first gate oxide layer, the second gate oxide layer having a thickness less than a thickness of the first gate oxide layer; and
forming a gate pattern over the field oxide layer, the first gate oxide layer, the second gate oxide layer, and part of the STI layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first gate oxide layer is in contact with an end portion of the field oxide.

### Claim 17 (depends on 15)

The method of claim 15, wherein an edge portion of the field oxide layer is in contact with an the STI layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein the gate pattern covers an entire width of the field oxide layer, the entire first gate oxide layer, and the entire second gate oxide layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein the STI layer has a depth less than 150 nm.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the field oxide layer comprises:
sequentially forming an oxide layer and a nitride layer on or over the substrate and the STI layer;
patterning the nitride layer and the oxide layer to expose a portion of the substrate adjacent to the STI layer to define a field oxide region; and
oxidizing the exposed portion of the substrate.