# US 2013/0154013 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2013/0154013 A1
- Document ID: US20130154013A1
- Status: Published application
- Kind: A1
- Application number: 13/331,574
- Filed: 2011-12-20
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Elpida Memory, Inc.
- Inventors: Mika NISHISAKA
- Web page: https://patentgrep.com/patent/US20130154013A1

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device is provided, which includes a circuit including a first MOS transistor having a gate connected to a first signal line, a second MOS transistor having a gate connected to a second signal line, and the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line, wherein channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms source and drain regions of the MOS transistors.

## Claims

### Claim 1

A semiconductor device comprising:
first and second MOS transistors, each MOS transistor comprising source and drain regions formed on a main surface of a semiconductor substrate, a channel region sandwiched between the source and drain regions, and a gate electrode provided over the channel region through a gate insulating film; and
a circuit comprising the first MOS transistor whose gate is connected to a first signal line and the second MOS transistor whose gate is connected to a second signal line, the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line,
wherein the channel regions of the first and second MOS transistors include no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms the source and drain regions.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the circuit is a sense amplifier circuit of a DRAM.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the circuit is a current mirror differential amplifier circuit.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the gate insulating films of the first and second MOS transistors comprise a high-k gate insulating film.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the channel regions of the first and second MOS transistors contain a first impurity whose concentration has a maximum value at an area, which is deeper than the depth indicating the maximum concentration of the one conduction type impurity that forms the source and drain regions, and is simply decreased from the depth indicating the maximum value of the concentration of the first impurity toward the surface of the semiconductor substrate.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the first impurity comprises indium.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the concentration of the first impurity on the surface of the semiconductor substrate is equal to or lower than 1E17.

### Claim 8

A semiconductor device comprising:
a first MOS transistor comprising source and drain regions formed on a main surface of a semiconductor substrate, a channel region sandwiched between the source and drain regions and a gate electrode provided over the channel region through a gate insulating film; and
a circuit comprising the first MOS transistor whose gate electrode receives an input signal having an intermediate potential between a power supply potential and a ground potential, the circuit outputting an output signal according to the potential of the input signal,
wherein the channel region of the first MOS transistor includes no maximum impurity concentration at an area, which is shallower than a depth indicating a maximum concentration of one conduction type impurity that forms the source and drain regions.

### Claim 9

(canceled)

### Claim 10 (depends on 21)

The semiconductor device according to claim 21, wherein a width of the gate electrode of the first and second MOS transistors is larger than a width of the gate electrode of the third MOS transistor.

### Claim 11 (depends on 21)

The semiconductor device according to claim 21, wherein the circuit is a sense amplifier circuit of a DRAM.

### Claim 12 (depends on 21)

The semiconductor device according to claim 21, wherein the circuit is a current mirror differential amplifier circuit.

### Claim 13

(canceled)

### Claim 14 (depends on 23)

The semiconductor device according to claim 23, wherein the first impurity comprises indium.

### Claim 15

(canceled)

### Claim 16

A method of manufacturing a semiconductor device, which comprises first and second MOS transistors, each MOS transistor including source and drain regions formed on a main surface of a semiconductor substrate, a channel region sandwiched between the source and drain regions, and a gate electrode provided over the channel region through a gate insulating film; and a circuit comprising the first MOS transistor whose gate is connected to a first signal line and the second MOS transistor whose gate is connected to a second signal line, the circuit outputting an output signal according to a difference in potential between the first signal line and the second signal line, the method comprising no step of implanting one conduction type impurity into the channel regions of the first and second MOS transistors so that a concentration of the one conduction type impurity has a maximum value at an area, which is shallower than a depth indicating the maximum concentration of the other conduction type impurity that forms the source and drain regions.

### Claim 17 (depends on 16)

The method of manufacturing a semiconductor device according to claim 16, further comprising implanting a first impurity into the channel regions of the first and second MOS transistors so that the maximum concentration of the first impurity is provided at an area, which is deeper than the depth indicating the maximum concentration of the one conduction type impurity that forms the source and drain regions, and that the channel regions of the first and second MOS transistors have a profile in which the concentration of the first impurity is simply decreased from the depth indicating the maximum concentration of the first impurity toward the surface of the semiconductor substrate.

### Claim 18 (depends on 17)

The method of manufacturing a semiconductor device according to claim 17, wherein the first impurity is ion species having a mass number of 49 or more.

### Claim 19 (depends on 17)

The method of manufacturing a semiconductor device according to claim 17, wherein the first impurity is indium.

### Claim 20 (depends on 17)

The method of manufacturing a semiconductor device according to claim 17, wherein the concentration of the first impurity at the surface of the semiconductor substrate is equal to or lower than 1E17.

### Claim 21 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a third MOS transistor including source and drain regions formed on the main surface of the semiconductor substrate, a channel region sandwiched between the source and drain regions and a gate electrode provided over the channel region through a gate insulating film;
wherein the channel region of the third MOS transistor contains a second impurity whose concentration has a maximum value at a second depth and is simply decreased from the second depth toward the surface of the semiconductor substrate.

### Claim 22 (depends on 21)

The semiconductor device according to claim 21, wherein the channel region of the third MOS transistor further contains a first impurity whose concentration has a maximum value at a first depth and is simply decreased from the first depth toward the surface of the semiconductor substrate.

### Claim 23 (depends on 21)

The semiconductor device according to claim 21, wherein the channel regions of the first, second, and third MOS transistors contains a first impurity whose concentration has a maximum value at a first depth, which is deeper than the second depth, and is simply decreased from the first depth toward the surface of the semiconductor substrate.