# US 2013/0154012 A1 · Manufacturing method for semiconductor device having metal gate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154012 A1 - Document ID: US20130154012A1 - Status: Published application - Kind: A1 - Application number: 13/326,342 - Filed: 2011-12-15 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: United Microelectronics Corp. - Inventors: Ssu-I Fu; Wen-Tai Chiang; Ying-Tsung Chen; Shih-Hung Tsai; Chien-Ting Lin; Chi-Mao Hsu; Chin-Fu Lin - Web page: https://patentgrep.com/patent/US20130154012A1 ## CPC - H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T} - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 84/0172: {Manufacturing their gate conductors} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. ## Claims ### Claim 1 A manufacturing method for semiconductor device having metal gate, comprising steps of: providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench and the multiple metal layer being exposed in the second gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. ### Claim 2 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein the first semiconductor device comprises a first conductivity type and the second semiconductor device comprises a second conductivity type, and the first conductivity type and the second conductivity type are complementary. ### Claim 3 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein the multiple metal layer comprises at least a bottom barrier layer and an etch stop layer. ### Claim 4 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein the step of forming the first work function metal layer in the first gate trench further comprises: forming the first work function metal layer on the substrate; forming a first patterned mask on the substrate, the first patterned mask exposing at least a portion of the first work function metal layer in the second gate trench; and removing the exposed first work function metal layer. ### Claim 5 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein the first pull back step further comprises: forming a second patterned mask respectively in the first gate trench and the second gate trench, a surface of the second patterned mask being lower than openings of the first gate trench and the second gate trench; and removing the exposed first work function metal layer from the first gate trench and the exposed multiple metal layer from the second gate trench simultaneously. ### Claim 6 (depends on 5) The manufacturing method for semiconductor device having metal gate according to claim 5, wherein a U-shaped first work function metal layer is formed in the first gate trench and a U-shaped multiple metal layer is formed in the second gate trench after performing the first pull back step. ### Claim 7 (depends on 6) The manufacturing method for semiconductor device having metal gate according to claim 6, wherein topmost portions of the U-shaped first work function metal layer and topmost portions of the U-shaped multiple metal layer are lower than the openings of the first gate trench and the second gate trench. ### Claim 8 (depends on 7) The manufacturing method for semiconductor device having metal gate according to claim 7, wherein the high-k gate dielectric layer is exposed on the substrate, at the opening of the first gate trench, and at the opening of the second gate trench after performing the first pull back step. ### Claim 9 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein the first pull back step further comprises: forming a second patterned mask filling up the second gate trench on the substrate, a surface of the second patterned mask being lower than an opening of the first gate trench; and removing the exposed the first work function metal layer from the first gate trench. ### Claim 10 (depends on 9) The manufacturing method for semiconductor device having metal gate according to claim 9, wherein the multiple metal layer in the second gate trench is protected by the second patterned mask. ### Claim 11 (depends on 9) The manufacturing method for semiconductor device having metal gate according to claim 9, wherein a U-shaped first work function metal layer is formed in the first gate trench after performing the first pull back step. ### Claim 12 (depends on 11) The manufacturing method for semiconductor device having metal gate according to claim 11, wherein topmost portions of the U-shaped first work function metal layer are lower than the opening of the first gate trench. ### Claim 13 (depends on 12) The manufacturing method for semiconductor device having metal gate according to claim 12, wherein the high-k gate dielectric layer is exposed at the opening of the first gate trench after performing the first pull back step. ### Claim 14 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein the second pull back step further comprises: forming a third patterned mask in the first gate trench and the second gate trench, a surface of the third patterned mask being lower than openings of the first gate trench and second gate trench; and removing the exposed second work function metal layer from the first gate trench and the second gate trench simultaneously. ### Claim 15 (depends on 14) The manufacturing method for semiconductor device having metal gate according to claim 14, wherein a U-shaped second work function metal layer is formed in the first gate trench and the second gate trench after performing the second pull back step. ### Claim 16 (depends on 15) The manufacturing method for semiconductor device having metal gate according to claim 15, wherein topmost portions of the U-shaped second work function metal layer are lower than the openings of the first gate trench and the second gate trench. ### Claim 17 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein topmost portions of the second work function metal layer, topmost portions of the first work function metal layer, and topmost portions of the multiple metal layer are coplanar after performing the second pull back step. ### Claim 18 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, wherein topmost portions of the second work function metal layer and topmost portions of the first work function metal layer are non-coplanar after performing the second pull back step. ### Claim 19 (depends on 18) The manufacturing method for semiconductor device having metal gate according to claim 18, wherein the topmost portions of the first work function metal layer in the first gate trench and topmost portions of the multiple metal layer in the first gate trench are coplanar, and the topmost portions of the second work function metal layer in the second gate trench and topmost portions of the multiple metal layer in the second gate trench are coplanar. ### Claim 20 (depends on 1) The manufacturing method for semiconductor device having metal gate according to claim 1, further comprising forming a filling metal layer respectively in the first gate trench and the second gate trench after performing the second pull back step. ### Claim 21 A semiconductor device and metal gates comprising: a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; a gate dielectric layer formed in the first gate trench and the second gate trench, respectively; a first U-shaped metal layer formed in the first gate trench and the second gate trench, and topmost portions of the first U-shaped metal layer being lower than openings of the first gate trench and the second gate trench; a second U-shaped metal layer formed in the first gate trench and the second gate trench, topmost portions of the second U-shaped metal layer being lower than openings of the first gate trench and the second gate trench, and the topmost portions of the first U-shaped metal layer and the topmost portions of the second U-shaped metal layer being un-coplanar; and a third U-shaped metal layer formed in the first gate trench and between the first U-shaped metal layer and the second U-shaped metal layer, topmost portions of the third U-shaped metal layer being lower than openings of the first gate trench and the second gate trench, and the topmost portions of the third U-shaped metal layer and the topmost portions of the second U-shaped metal layer being un-coplanar. ### Claim 22 (depends on 21) The semiconductor device according to claim 21, wherein the gate dielectric layer comprises a high dielectric constant (high-k) gate dielectric layer. ### Claim 23 (depends on 22) The semiconductor device according to claim 22, wherein the high-k gate dielectric layer covers sidewalls and bottoms of the first gate trench and the second gate trench. ### Claim 24 (depends on 21) The semiconductor device according to claim 21, wherein the first U-shaped metal layer comprises at least a bottom barrier layer and an etch stop layer. ### Claim 25 (depends on 21) The semiconductor device according to claim 21, wherein the second U-shaped metal layer comprises a first work function metal layer, the third U-shaped metal layer comprises a second work function metal layer, and the first work function metal layer and the second work function metal layer are complementary. ### Claim 26 (depends on 21) The semiconductor device according to claim 21, wherein the topmost portions of the first U-shaped metal layer and the topmost portions of the third U-shaped metal layer are coplanar. ### Claim 27 (depends on 21) The semiconductor device according to claim 21 further comprising a filling metal layer formed in the first gate trench and the second gate trench, the filling metal layer covering the second U-shaped metal layer and filling up the first gate trench and the second gate trench.