# US 2013/0154010 A1 · Integrated Circuit Device, System, and Method of Fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154010 A1 - Document ID: US20130154010A1 - Status: Published application - Kind: A1 - Application number: 13/561,597 - Filed: 2012-07-30 - Published: 2013-06-20 - Earliest claimed: 2006-05-15 - Assignees: Carnegie Mellon University - Inventors: Wojciech P. Maly - Web page: https://patentgrep.com/patent/US20130154010A1 ## CPC - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/0411: {of FETs having floating gates} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor portion, defining a top surface and a bottom surface, having a cross-sectional shape in a plane parallel with said top and bottom surfaces which is wider at opposite ends thereof and which tapers to a narrower portion between said ends, said narrower portion extending from said top surface to said bottom surface. a first gate portion connected to said semiconductor portion on one side of at said narrower portion, extending from said top surface to said bottom surface; a second gate portion connected to said semiconductor portion at the opposite sides of said narrower portion, extending from said top surface to said bottom surface; and at least three metal terminals selected from a group consisting of: a first terminal connected to one wider end of said semiconductor portion; a second terminal connected to the other wider end of said semiconductor portion; a third terminal connected to the first gate portion; and a fourth terminal connected to the second gate portion; wherein said top surface and said bottom surface define a height therebetween, and further wherein said at least three metal terminals extend along said height of said device such as to be accessible from said top surface and said bottom surface. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein: said semiconductor portion is single crystal silicon; and said first and second gate portions are polysilicon. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein: said semiconductor portion is doped silicon; said first gate portion is doped silicon; and said second gate portion is doped silicon; wherein the doping in said semiconductor portion is different than the doping in said first and second gate portions. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein said device includes the first, second, third and fourth terminals. ### Claim 5 (depends on 1) The semiconductor device of claim 1 wherein said first and second gate portions are separated from said semiconductor portion by a layer of dielectric material. ### Claim 6 (depends on 1) The semiconductor device of claim 1 wherein said at least three metal terminals extend above said top surface and below said bottom surface. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising: a top interconnect connected to at least one of said terminals at said top surface; and a bottom interconnect connected to at least one of said terminals at said bottom surface. ### Claim 8 (depends on 1) The device of claim 1 wherein the cross-sectional shape of said semiconductor device in a plan parallel to said top and bottom surfaces is square. ### Claim 9 (depends on 1) The semiconductor device of claim 1 wherein said at least three terminals each have a circular cross sectional shape in a plane parallel to said top and bottom surfaces. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein: said narrower portion of said semiconductor portion is doped silicon; and said wider end portions of said semiconductor portion is doped silicon; wherein the doping in said narrower portion is different than the doping in said wider end portions. ### Claim 11 (depends on 8) The semiconductor device of claim 8 wherein said at least three terminals are all evenly spaced from adjacent terminals. ### Claim 12 (depends on 1) The semiconductor device of claim 1 wherein said device is a field effect transistor and further wherein said first terminal is a source terminal, said second terminal is a drain terminal and said third and fourth terminals are gate terminals. ### Claim 13 (depends on 12) The semiconductor device of claim 12 further comprising: a layer of dielectric material between said first gate portion and said semiconductor portion and a between said second gate portion and said semiconductor portion; wherein said first and second gate portions are polysilicon and said first semiconductor portion is selected from a group consisting of n-doped silicon and p-doped silicon; ### Claim 14 (depends on 13) The device of claim 13 further comprising: a portion of said first semiconductor portion adjacent said first gate portion and a portion of said semiconductor portion adjacent said second gate portion being selected from a group consisting of “n−” doped silicon and “p−” doped silicon; and ### Claim 15 (depends on 1) The semiconductor device of claim 1 wherein said device is a bi-polar transistor and further wherein said first and second terminals are base terminals, said first gate portion is an emitter and said second gate portion is a collector. ### Claim 16 (depends on 15) The semiconductor device of claim 15 wherein said device is a N-P-N bi-polar transistor: wherein said first and second gate portions are polysilicon; wherein said semiconductor portion is p-doped silicon; and wherein said semiconductor portion has a layer of n-doped silicon adjacent said first gate portion and said second gate portion. ### Claim 17 (depends on 15) The semiconductor device of claim 15 wherein said device is a P-N-P bi-polar transistor: wherein said first and second gate portions are polysilicon; wherein said semiconductor portion is n-doped silicon; and wherein said semiconductor portion has a layer of p-doped silicon adjacent said first gate portion and said second gate portion. ### Claim 18 (depends on 8) The device of claim 8 wherein each side of said device is approximately 300 nm in length. ### Claim 19 (depends on 12) The semiconductor device of claim 12 wherein said first terminal is a source, said second terminal is a drain, said third terminal is a first gate and further comprising: an electrical insulator between said second gate portion and said semiconductor portion; wherein said second gate portion may accumulate and store a charge which is determined by biasing voltages applied to said first terminal, said second terminal and said first gate, said biasing voltages resulting in current passing through said electrical insulator, thereby providing said device with an electrically programmable threshold voltage.