# US 2013/0154009 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154009 A1 - Document ID: US20130154009A1 - Status: Published application - Kind: A1 - Application number: 13/767,396 - Filed: 2013-02-14 - Published: 2013-06-20 - Earliest claimed: 2010-05-18 - Assignees: Panasonic Corporation - Inventors: Tomoaki IKEGAMI; Kazuyuki NAKANISHI; Masaki TAMARU - Web page: https://patentgrep.com/patent/US20130154009A1 ## CPC - H10D 89/10: Integrated device layouts - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 84/998: {Input and output buffer/driver structures} - H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] - H10D 89/611: {using diodes as protective elements} - H10D 84/907: {CMOS gate arrays} - H10D 89/931: {characterised by the dispositions of the protective arrangements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. ## Claims ### Claim at position 1 1-8. (canceled) ### Claim 9 A semiconductor device, comprising: a standard cell having three or more gate patterns extending in a first direction and arranged at an equal pitch along a second direction orthogonal to the first direction; and a diode cell located next to the standard cell in the first direction, wherein: the gate patterns included in the standard cell terminate near a cell boundary between the standard cell and the diode cell, with respective end portions located at a same position in the first direction and having an equal width in the second direction, the diode cell includes: a plurality of diffusion region patterns; and a plurality of opposite end portions formed of a gate pattern, which are located near the cell boundary and opposed to the end portions of the gate patterns included in the standard cell, and at least one of the plurality of diffusion region patterns functions as a diode. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the diode cell includes a plurality of gate patterns extending in the first direction and respectively having the plurality of opposite end portions. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the diode cell includes a second gate pattern extending in the second direction and connected to the plurality of gate patterns such that a grid gate pattern is formed in the diode cell. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the plurality of gate patterns included in the diode cell are arranged at a pitch equal to the pitch at which the gate patterns included in the standard cell are arranged in the second direction, with the plurality of opposite end portions located at a same position in the first direction and having an equal width in the second direction. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the plurality of diffusion region patterns included in the diode cell are arranged between the plurality of gate patterns at an equal pitch in the second direction, and have an equal width in the second direction. ### Claim 14 (depends on 9) The semiconductor device of claim 9, wherein the gate pattern included in the diode cell is a dummy pattern. ### Claim 15 (depends on 10) The semiconductor device of claim 10, wherein in the diode cell, the plurality of diffusion region patterns are arranged so as to sandwich at least one of the plurality of gate patterns, and the gate pattern sandwiched between the plurality of diffusion region patterns functions as a gate of a transistor. ### Claim 16 (depends on 9) The semiconductor device of claim 9, wherein: the diode cell has a dummy pattern which forms at least part of the plurality of opposite end portions, the dummy pattern includes a pattern body extending in the second direction, and two or more protrusions protruding from the pattern body toward the standard cell in the first direction, and the protrusions form the opposite end portions. ### Claim 17 (depends on 9) The semiconductor device of claim 9, wherein the plurality of diffusion region patterns are connected to each other by a metal wire in an upper layer. ### Claim 18 (depends on 9) The semiconductor device of claim 9, wherein the diode cell has an input terminal and the input terminal is connected to the at least one of the plurality of diffusion region patterns. ### Claim 19 (depends on 9) The semiconductor device of claim 9, wherein the plurality of diffusion region patterns have an equal length in the first direction. ### Claim 20 (depends on 10) The semiconductor device of claim 10, wherein the plurality of gate patterns in the diode cell have an equal length in the first direction. ### Claim 21 (depends on 20) The semiconductor device of claim 20, wherein the plurality of gate patterns in the diode cell are dummy patterns. ### Claim 22 (depends on 9) The semiconductor device of claim 9, wherein the plurality of opposite end portions are located at the same position in the first direction. ### Claim 23 (depends on 9) The semiconductor device of claim 9, wherein the plurality of diffusion region patterns are arranged at an equal pitch along the second direction. ### Claim 24 (depends on 9) The semiconductor device of claim 9, wherein the plurality of diffusion region patterns have an equal width in the second direction. ### Claim 25 (depends on 9) The semiconductor device of claim 9, wherein the end portions of the plurality of diffusion regions are located at a same position in the first direction. ### Claim 26 (depends on 10) The semiconductor device of claim 10, wherein the plurality of diffusion regions are connected together and sandwiching the gate patterns.