# US 2013/0154008 A1 · Isolated epitaxial modulation device

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- Number: US 2013/0154008 A1
- Document ID: US20130154008A1
- Status: Published application
- Kind: A1
- Application number: 13/717,917
- Filed: 2012-12-18
- Published: 2013-06-20
- Earliest claimed: 2010-08-20
- Assignees: Intersil Americas Inc.
- Inventors: Yu Li; Steven Howard Voldman
- Web page: https://patentgrep.com/patent/US20130154008A1

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10D 89/815: {involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 72/90: Bond pads, in general
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

## Claims

### Claim 1

An isolated epitaxial modulation device comprising:
a substrate;
a barrier structure formed on the substrate;
an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure;
a semiconductor device, the semiconductor device located in the isolated epitaxial region;
a modulation network formed on the substrate and electrically coupled to the semiconductor device;
a bond pad; and
a ground pad;
wherein the isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad; and
wherein the semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

### Claim 2 (depends on 1)

The isolated epitaxial modulation device of claim 1, wherein the semiconductor device comprises one of a metal oxide semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), and a laterally diffused metal oxide semiconductor (LDMOS) device.

### Claim 3 (depends on 1)

The isolated epitaxial modulation device of claim 1, wherein the modulation network comprises a resistor-capacitor (RC) discriminator and a transistor.

### Claim 4 (depends on 1)

The isolated epitaxial modulation device of claim 1 wherein the semiconductor device comprises:
a plurality of parallel transistors configured to shunt electrostatic discharge (ESD) current, each transistor having a gate, a drain region, and a source region;
wherein the isolated epitaxial modulation device further comprises:
a conductive body ring located in the isolated epitaxial region and surrounding the plurality of fingers, the conductive body ring having one or more body ties, wherein each body tie is located between adjacent source regions of the plurality of fingers; and
a ground ring surrounding and coupled to the body ring.

### Claim 5 (depends on 4)

The isolated epitaxial modulation device of claim 4, wherein the ground ring and the ground pad are coupled to the same ground potential.

### Claim 6 (depends on 1)

The isolated epitaxial modulation device of claim 1, wherein the bond pad is implemented as one of an input pad, an output pad, an input/output (I/O) pad, or a power pad.

### Claim 7 (depends on 1)

The isolated epitaxial modulation device of claim 1, wherein the semiconductor device is implemented in one of a complementary metal oxide semiconductor (CMOS) technology, a bipolar junction transistor-CMOS (BiCMOS) technology, a silicon on insulator (SOI) technology, silicon on diamond (SOD), silicon on sapphire (SOS) or a bipolar-CMOS-DMOS (BCD) technology.

### Claim 8 (depends on 1)

The isolated epitaxial modulation device of claim 1, wherein the barrier structure comprises:
a buried layer; and
a well coupled to the buried layer to enclose the isolated epitaxial region.

### Claim 9 (depends on 8)

The isolated epitaxial modulation device of claim 8, wherein the well comprises one of a silicon metallurgical junction structure, shallow trench isolation (STI) structure, deep trench (DT) structure, through wafer via (TWV) structure, or through silicon vias (TSV) structure.

### Claim 10

An integrated circuit comprising:
a substrate;
processing circuitry formed on the substrate;
a barrier structure formed on the substrate;
an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure;
a semiconductor device, the semiconductor device located in the isolated epitaxial region;
a modulation network formed on the substrate and electrically coupled to the semiconductor device; and
a signal pad electrically coupled to the isolated epitaxial region;
wherein the semiconductor device and the epitaxial modulation network are configured to protect the processing circuitry from current spikes.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the semiconductor device includes a multi-finger n-channel metal oxide semiconductor (NMOS), each of the fingers comprising a gate, a drain region and a source region.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, further comprising a conductive structure located in the isolated epitaxial region, the conductive structure coupled to a ground potential and comprising:
a conductive ring surrounding the semiconductor device; and
a plurality of conductive strips coupled to the conductive ring, each conductive strip located between adjacent source regions of the plurality of fingers.

### Claim 13 (depends on 10)

The integrated circuit of claim 10, wherein the modulation network comprises a resistor, a capacitor and a transistor.

### Claim 14 (depends on 10)

The integrated circuit of claim 10, further comprising a ground pad, the ground pad electrically coupled to the isolated epitaxial region.

### Claim 15 (depends on 10)

The integrated circuit of claim 10, further comprising a power pad, the power pad electrically coupled to the isolated epitaxial region.

### Claim 16 (depends on 10)

The integrated circuit of claim 10, wherein the barrier structure comprises an oxide insulating material.

### Claim 17

A system comprising:
processing circuitry;
a power converter coupled to a power source and configured to convert power from the power source to a power level or a polarity usable by the processing circuitry; and
one or more isolated epitaxial modulation devices configured to modulate an input voltage, each of the one or more isolated epitaxial modulation devices coupled to a respective one of the processing circuitry and the power converter;
wherein each of the one or more isolated epitaxial modulation devices comprises:
a substrate;
a barrier structure formed on the substrate;
an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure;
a semiconductor device, the semiconductor device located in the isolated epitaxial region;
a modulation network formed on the substrate and electrically coupled to the semiconductor device; and
a bond pad coupled to the isolated epitaxial region;
wherein the semiconductor device and the epitaxial modulation network are configured to modulate the input voltage.

### Claim 18 (depends on 17)

The system of claim 17, wherein the semiconductor device comprises a metal oxide semiconductor field-effect transistor (MOSFET).

### Claim 19 (depends on 17)

The system of claim 17, wherein the modulation network comprises a transistor coupled between the bond pad and a ground potential.

### Claim 20 (depends on 17)

The system of claim 17, wherein the semiconductor device comprises:
a plurality of parallel transistors, each transistor having a gate, a drain region, and a source region;
wherein each of the isolated epitaxial modulation devices further comprises a conductive structure located in the isolated epitaxial region, the conductive structure comprising:
a conductive ring surrounding the plurality of parallel transistors; and
a plurality of conductive strips coupled to the conductive ring, each conductive strip located between adjacent source regions of the plurality of parallel transistors.

### Claim 21 (depends on 17)

The system of claim 17, wherein the one or more isolated epitaxial modulation devices comprises a first isolated epitaxial modulation device coupled to the power converter and a second isolated epitaxial modulation device coupled to the processing circuitry;
wherein the bond pad in the first isolated epitaxial modulation device comprises a power pad and the bond pad in the second isolated epitaxial modulation device comprises a signal pad.

### Claim 22 (depends on 17)

The system of claim 17, wherein the power source comprises a battery.