# US 2013/0154006 A1 · Finfet with vertical silicide structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0154006 A1
- Document ID: US20130154006A1
- Status: Published application
- Kind: A1
- Application number: 13/649,284
- Filed: 2012-10-11
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: International Business Machines Corporation
- Inventors: Veeraraghavan S. Basker; Chung-Hsun Lin; Tenko Yamashita; Chun-Chen Yeh
- Web page: https://patentgrep.com/patent/US20130154006A1

## CPC

- H10D 86/215: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.

## Claims

### Claim 1

A method of forming a MOSFET, comprising:
providing a substrate with a plurality of fins;
forming a gate stack above the substrate wherein the gate stack has at least one sidewall;
forming an off-set spacer adjacent the gate stack sidewall;
growing an epitaxial film which merges the fins to form an epi-merge layer;
forming a field oxide layer adjacent to at least a portion of the off-set spacer;
removing a portion of the field oxide layer to expose a portion of the epi-merge-layer;
removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region; and
forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of removing a portion of the epi-merge layer also forms an epi-merge field region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the field oxide layer is formed directly on the epi-merge layer.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
forming a silicide with the epi-merge field region to form a field silicide.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
implanting the fins with a dopant to from doped extensions under the off-set spacer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
implanting the epi-merge layer with a dopant to create a source and a drain.

### Claim 7 (depends on 1)

The method of claim 1, wherein the two silicide sidewalls are perpendicular to the substrate.

### Claim 8

A MOSFET, comprising:
a substrate with a plurality of fins and a buried insulator region, the substrate having an epi-merge region;
a gate stack above the buried insulator region wherein the gate stack has at least one sidewall;
an off-set spacer adjacent the gate stack sidewall;
a field oxide layer adjacent at least a portion of the off-set spacer and above the below the epi-merge region of the substrate; and
a silicide structure within the epi-merge region having a silicide layer and two silicide sidewalls.

### Claim 9 (depends on 8)

The MOSFET of claim 8, wherein the two silicide sidewalls are perpendicular to the substrate.

### Claim 10 (depends on 9)

The MOSFET of claim 9, wherein the silicide sidewalls have a height from about 5 nm to about 50 nm.

### Claim 11 (depends on 9)

The MOSFET of claim 9, wherein a distance between the silicide sidewalls and the gate stack sidewall is about 10 nm to about 50 nm.

### Claim 12

A MOSFET, comprising:
a source;
a drain;
a gate stack interposed between the source and the drain;
a channel under the gate stack and interposed between the source and the drain; and
a silicide structure on the source and drain wherein in a portion of the silicide structure is perpendicular to the channel.

### Claim 13 (depends on 12)

The MOSFET of claim 12, wherein the silicide structure comprises a silicide layer parallel to the channel and two silicide sidewalls perpendicular to the channel.

### Claim 14 (depends on 13)

The MOSFET of claim 13, wherein the silicide sidewalls have a height from about 5 nm to about 50 nm.

### Claim 15 (depends on 12)

The MOSFET of claim 12, wherein a distance between the silicide sidewalls and the gate stack sidewall is about 10 nm to about 50 nm.