# US 2013/0154005 A1 · Soi finfet with recessed merged fins and liner for enhanced stress coupling

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- Number: US 2013/0154005 A1
- Document ID: US20130154005A1
- Status: Published application
- Kind: A1
- Application number: 13/606,893
- Filed: 2012-09-07
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: International Business Machines Corporation
- Inventors: Veeraraghavan S. Basker; Huiming Bu; Effendi Leobandung; Theodorus E. Standaert; Tenko Yamashita; Chun-Chen Yeh
- Web page: https://patentgrep.com/patent/US20130154005A1

## CPC

- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SW substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.

## Claims

### Claim 1

A MOSFET, comprising:
a substrate with a plurality of fins and a buried insulator region;
a gate stack above the buried insulator region wherein the gate stack has at least one sidewall;
an off-set spacer adjacent the gate stack sidewall;
a dummy spacer adjacent at least a portion of the off-set spacer;
an epi-merge spacer region above the insulator region and below the dummy spacer;
a field silicide above the buried insulator region; and
a stress liner above the field silicide.

### Claim 2 (depends on 1)

The MOSFET of claim 1, further comprising:
an epi-merge sidewall wherein the epi-merge sidewall is a sidewall of the epi-merge spacer region.

### Claim 3 (depends on 2)

The MOSFET of claim 2, further comprising:
a sidewall silicide formed with the epi-merge sidewall.

### Claim 4 (depends on 3)

The MOSFET of claim 3, wherein the sidewall silicide has a height from about 5 nm to about 50 nm.

### Claim 5 (depends on 3)

The MOSFET of claim 3, wherein a distance between the sidewall silicide and the gate stack sidewall is about 10 nm to about 50 nm.

### Claim 6 (depends on 1)

The MOSFET of claim 1, wherein the epi-merge-spacer region is adjacent to the off-set spacer.

### Claim 7 (depends on 1)

The MOSFET of claim 1, further comprising:
an epi-merge field region between the field silicide and the buried insulator region, wherein the epi-merge-spacer region has a thickness which is greater than a thickness of the epi-merge-field region.

### Claim 8 (depends on 1)

The MOSFET of claim 1, wherein the epi-merge-spacer region has a thickness from about 10 nm to about 80 nm.

### Claim 9 (depends on 1)

The MOSFET of claim 1, wherein the epi-merge-field region has a thickness of about 5 nm to about 30 nm.

### Claim 10 (depends on 1)

The MOSFET of claim 1, wherein the stress liner is above the gate stack.

### Claim 11 (depends on 1)

The MOSFET of claim 1, wherein a portion of one of the plurality of fins is between the insulator region and the gate stack.

### Claim 12 (depends on 3)

The MOSFET of claim 3, wherein the off-set spacer is above the fin portion.

### Claim 13 (depends on 3)

The MOSFET of claim 3, wherein the epi-merge-spacer region is adjacent to the fin portion.

### Claim 14

A MOSFET, comprising:
a source;
a drain;
a gate stack interposed between the source and the drain;
a channel under the gate stack and interposed between the source and the drain;
a silicide layer on the source and drain wherein in a portion of the silicide layer is perpendicular to the channel; and
a stress liner above the gate stack and the substrate.