# US 2013/0154003 A1 · Asymmetric anti-halo field effect transistor

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- Number: US 2013/0154003 A1
- Document ID: US20130154003A1
- Status: Published application
- Kind: A1
- Application number: 13/329,440
- Filed: 2011-12-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: International Business Machines Corporation
- Inventors: James W. Adkisson; Brent A. Anderson; Andres Bryant; Edward J. Nowak
- Web page: https://patentgrep.com/patent/US20130154003A1

## CPC

- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D 30/0218: {having pocket halo regions selectively formed at the sides of the gates}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0225: {using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask.

## Claims

### Claim 1

A method of forming an integrated circuit structure, said method comprising:
implanting a first compensating implant into a substrate;
patterning a mask on said first compensating implant in said substrate, said mask including an opening exposing a channel location of said substrate;
implanting a second compensating implant into said channel location of said substrate through said opening at an angle that is offset from perpendicular to a top surface of said substrate, said second compensating implant being positioned closer to a first side of said channel location relative to an opposite second side of said channel location, and said second compensating implant comprising a material having the same doping polarity as said semiconductor channel implant;
forming a gate conductor above said channel location of said substrate in said opening of said mask;
removing said mask to leave said gate conductor standing on said channel location of said substrate; and
implanting source and drain implants into source/drain regions of said substrate adjacent to said channel location.

### Claim 2 (depends on 1)

The method according to claim 1, said first compensating implant and said second compensating implant comprising different materials.

### Claim 3 (depends on 1)

The method according to claim 1, said first compensating implant and said second compensating implant altering a threshold voltage rollup characteristic of said integrated circuit structure.

### Claim 4 (depends on 1)

The method according to claim 1, said first compensating implant being uniform across a width and length of said channel location.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising forming shallow trench isolation regions into said substrate before implanting said first compensating implant.

### Claim 6 (depends on 1)

The method according to claim 1, said substrate comprising a silicon-on-insulator substrate.

### Claim 7

A method of forming an integrated circuit structure, said method comprising:
implanting a first compensating implant into a substrate;
patterning a mask on said first compensating implant in said substrate, said mask including an opening exposing a channel location of said substrate;
implanting a second compensating implant into said channel location of said substrate through said opening at an angle that is offset from perpendicular to a top surface of said substrate, said second compensating implant being positioned closer to a first side of said channel location relative to an opposite second side of said channel location, and said second compensating implant comprising a material having the same doping polarity as said semiconductor channel implant;
forming a gate conductor above said channel location of said substrate in said opening of said mask;
removing said mask to leave said gate conductor standing on said channel location of said substrate;
implanting source and drain extensions into source/drain regions of said substrate adjacent to said channel location using said gate conductor as an alignment device;
forming sidewall spacers on said gate conductor; and
implanting source and drain implants into said source/drain regions of said substrate using said sidewall spacers as an alignment device.

### Claim 8 (depends on 7)

The method according to claim 7, said first compensating implant and said second compensating implant comprising different materials.

### Claim 9 (depends on 7)

The method according to claim 7, said first compensating implant and said second compensating implant altering a threshold voltage rollup characteristic of said integrated circuit structure.

### Claim 10 (depends on 7)

The method according to claim 7, said first compensating implant being uniform across a width and length of said channel location.

### Claim 11 (depends on 7)

The method according to claim 7, further comprising forming shallow trench isolation regions into said substrate before implanting said first compensating implant.

### Claim 12 (depends on 7)

The method according to claim 7, said substrate comprising a silicon-on-insulator substrate.

### Claim 13

A method of forming an integrated circuit structure, said method comprising:
implanting a first compensating implant into a substrate;
after implanting said first compensating implant, patterning a mask on said first compensating implant in said substrate, said mask including an opening exposing a channel location of said substrate;
after patterning said mask, forming a gate insulator material on said mask and said channel location of said substrate;
after patterning said mask, implanting a second compensating implant into said channel location of said substrate through said opening at an angle that is offset from perpendicular to a top surface of said substrate, said second compensating implant being positioned closer to a first side of said channel location relative to an opposite second side of said channel location, and said second compensating implant comprising a material having the same doping polarity as said semiconductor channel implant;
after implanting said second compensating implant, forming a gate conductor on said channel location of said substrate in said opening of said mask;
after forming said gate conductor, removing said mask to leave said gate conductor standing on said channel location of said substrate, a size of said opening in said mask controls a size of said second compensating implant within said channel location of said substrate, without affecting a size of said first compensating implant within said channel location of said substrate;
after removing said mask, implanting source and drain extensions into source/drain regions of said substrate adjacent to said channel location using said gate conductor as an alignment device;
after removing said mask, forming sidewall spacers on said gate conductor; and
after forming said sidewall spacers, implanting source and drain implants into said source/drain regions of said substrate using said sidewall spacers as an alignment device.

### Claim 14 (depends on 13)

The method according to claim 13, said first compensating implant and said second compensating implant comprising different materials.

### Claim 15 (depends on 13)

The method according to claim 13, said first compensating implant and said second compensating implant altering a threshold voltage rollup characteristic of said integrated circuit structure.

### Claim 16 (depends on 13)

The method according to claim 13, said first compensating implant being uniform across a width and length of said channel location.

### Claim 17 (depends on 13)

The method according to claim 13, further comprising forming shallow trench isolation regions into said substrate before implanting said first compensating implant.

### Claim 18 (depends on 13)

The method according to claim 13, said substrate comprising a silicon-on-insulator substrate.

### Claim 19

An integrated circuit structure comprising:
a semiconductor channel implant extending into a substrate to a first depth;
a first compensating implant extending into said substrate to a second depth, said first depth being further from a top surface of said substrate relative to said second depth, said first compensating implant comprising a material having a different doping polarity than said semiconductor channel implant;
a gate insulator material on a channel location of said substrate;
a second compensating implant in said channel location of said substrate, said second compensating implant being positioned closer to a first side of said channel location relative to an opposite second side of said channel location, and said second compensating implant comprising a material having the same doping polarity as said semiconductor channel implant;
a gate conductor on said gate insulator material over said channel location of said substrate;
source and drain extensions in source/drain regions of said substrate adjacent to said channel location;
sidewall spacers on said gate conductor; and
source and drain implants in said source/drain regions of said substrate.

### Claim 20 (depends on 19)

The integrated circuit structure according to claim 19, said first compensating implant and said second compensating implant comprising different materials.

### Claim 21 (depends on 19)

The integrated circuit structure according to claim 19, said first compensating implant and said second compensating implant altering a threshold voltage rollup characteristic of said integrated circuit structure.

### Claim 22 (depends on 19)

The integrated circuit structure according to claim 19, said first compensating implant being uniform across a width and length of said channel location.

### Claim 23 (depends on 19)

The integrated circuit structure according to claim 19, further comprising shallow trench isolation regions in said substrate.

### Claim 24 (depends on 19)

The integrated circuit structure according to claim 19, said substrate comprising a silicon-on-insulator substrate.