# US 2013/0154002 A1 · FinFETs with Multiple Threshold Voltages

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- Number: US 2013/0154002 A1
- Document ID: US20130154002A1
- Status: Published application
- Kind: A1
- Application number: 13/328,936
- Filed: 2011-12-16
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Po-Chin Kuo; Hsien-Ming Lee
- Web page: https://patentgrep.com/patent/US20130154002A1

## CPC

- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01322: {the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 50/642: {Chemical etching}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.

## Claims

### Claim 1

A device comprising:
a substrate;
a semiconductor fin over the substrate;
a gate dielectric layer on a top surface and sidewalls of the semiconductor fin; and
a gate electrode spaced apart from the semiconductor fin by the gate dielectric layer, wherein the gate electrode comprises a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer, and wherein the top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first work function is higher than the second work function.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first work function is lower than the second work function.

### Claim 4 (depends on 1)

The device of claim 1, wherein the gate electrode comprises:
a first metal layer over and aligned to the semiconductor fin, wherein the first metal layer does not extend to sides of the semiconductor fin; and
a second metal layer comprising a first portion over and aligned to the semiconductor fin, and second portions extending on the sides of the semiconductor fin, wherein the first metal layer and the second metal layer comprise different materials.

### Claim 5 (depends on 4)

The device of claim 4 further comprising a capping layer over the dielectric layer and under the first and the second metal layers, wherein the first metal layer and the second metal layer both contact the capping layer.

### Claim 6 (depends on 5)

The device of claim 5, wherein the capping layer comprises titanium nitride.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first work function and the second work function have a difference greater than about 0.2 eV.

### Claim 8

A device comprising:
a substrate;
a semiconductor fin over the substrate, wherein the semiconductor fin is a part of a Fin Field-Effect Transistor (FinFET);
a gate dielectric layer on a top surface and sidewalls of the semiconductor fin; and
a gate electrode spaced apart from the semiconductor fin by the gate dielectric layer, wherein the gate electrode comprises:
a first metal layer over and aligned to the semiconductor fin, wherein the first metal layer does not comprise substantial portions that are lower than a top surface of the semiconductor fin; and
a second metal layer comprising a first portion over and aligned to the first metal layer, and second portions lower than the top surface of the semiconductor fin, wherein the first metal layer and the second metal layer comprise different materials, and wherein the first metal layer and the first portion of the second metal layer form a top portion of a gate electrode of the FinFET, and the second portions of the second metal layer form sidewall portions of the gate electrode of the FinFET.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first metal layer has a first work function, the second metal layer has a second work function, and wherein the first work function is greater than the second work function.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first metal layer has a first work function, the second metal layer has a second work function, and wherein the first work function is lower than the second work function.

### Claim 11 (depends on 8)

The device of claim 8 further comprising a capping layer over the dielectric layer and under the first and the second metal layers, wherein the first metal layer and the second metal layer both contact the capping layer.

### Claim 12 (depends on 11)

The device of claim 11, wherein the capping layer comprises titanium nitride.

### Claim 13

A method comprising:
forming a gate dielectric on a semiconductor fin, wherein the gate dielectric comprises a top portion over a top surface of the semiconductor fin, and sidewall portions on sidewalls of the semiconductor fin;
forming a first metal layer over the top portion of the gate dielectric, wherein the first metal layer does not comprise portions extending on the sidewall portions of the gate dielectric; and
forming a second metal layer, wherein the second metal layer comprises a first portion over the first metal layer, and second portions extending on the sidewall portions of the gate dielectric, and wherein the first and the second metal layers comprise different materials.

### Claim 14 (depends on 13)

The method of claim 13, wherein the step of forming the first metal layer is performed using a non-conformal disposition method.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second metal layer is formed using a conformal deposition method.

### Claim 16 (depends on 13)

The method of claim 13, wherein the step of forming the first metal layer comprises depositing the first metal layer, and preforming an etching step to remove portions of the first metal layer on the sidewall portions of the gate dielectric.

### Claim 17 (depends on 13)

The method of claim 13, wherein the first metal layer and the first portion of the second metal layer form a top portion of a gate electrode, and the second portions of the second metal layer form second portions of the gate electrode, and wherein the top portion of the gate electrode and the second portions of the gate electrode have different work functions.

### Claim 18 (depends on 13)

The method of claim 13 further comprising, after the step of forming the gate dielectric and before the step of forming the first metal layer, forming a capping layer over the gate dielectric, wherein the first and the second layers are both in contact with the capping layer.

### Claim 19 (depends on 18)

The method of claim 18 further comprising:
forming a dummy gate over the capping layer; and
removing the dummy gate, wherein the capping layer is exposed after the step of removing the dummy gate, and wherein the steps of forming the first metal layer and the second metal layer are performed after the step of removing the dummy gate.

### Claim 20 (depends on 13)

The method of claim 13, wherein the first metal layer and the second metal layer have a work function difference greater than about 0.1 eV.