# US 2013/0153996 A1 · Hybrid cmos nanowire mesh device and pdsoi device

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- Number: US 2013/0153996 A1
- Document ID: US20130153996A1
- Status: Published application
- Kind: A1
- Application number: 13/328,069
- Filed: 2011-12-16
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: International Business Machines Corporation
- Inventors: Josephine B. Chang; Leland Chang; Chung-Hsun Lin; Jeffrey W. Sleight
- Web page: https://patentgrep.com/patent/US20130153996A1

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- Y10S 977/762: Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
- Y10S 977/938: Field effect transistors, FETS, with nanowire- or nanotube-channel region
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.

## Claims

### Claim 1

A method of forming a hybrid semiconductor structure comprising:
providing a semiconductor on insulator substrate comprising a top semiconductor layer and a buried insulating layer;
providing a material stack on top of the top semiconductor layer, the material stack including alternating layers of semiconductor material and sacrificial material, wherein the bottommost layer of the patterned material stack is the top semiconductor layer of the semiconductor on insulator substrate;
providing a hard mask over the patterned material stack;
blocking the hard mask and material stack in a first portion of the semiconductor structure;
removing the hard mask and material stack in a second portion of the semiconductor structure while leaving a layer of the top semiconductor layer;
regrowing the layer of the top semiconductor layer into a thicker layer of the top semiconductor layer in the second portion of the semiconductor structure to form a partially depleted semiconductor on insulator (PDSOI) layer;
patterning the hard mask to form a plurality of hard mask structures in the first portion of the semiconductor structure;
forming a dummy gate over a central portion of each of said plurality of hard mask structures in the first portion of the semiconductor structure and over a central portion of the PDSOI layer in the second portion of the semiconductor structure;
forming a sacrificial material layer abutting the dummy gates in the first and second portions of the semiconductor structure;
removing the dummy gates to form a trench in the sacrificial material layer of each of the first and second portions of the semiconductor structure to expose the central portion of each of said plurality of hard mask structures in the first portion of the semiconductor structure and the central portion of the PDSOI layer in the second portion of the semiconductor structure;
blocking the second portion of the semiconductor structure;
etching a plurality of fins within the trench in the patterned material stack in the first portion of the semiconductor structure using the plurality of patterned hard masks as an etch mask;
removing the plurality of patterned hard masks in the first portion of the semiconductor structure;
removing each layer of sacrificial material within the trench in the first portion of the semiconductor structure to form a plurality of vertically stacked and vertically spaced apart semiconductor nanowires within the trench in the first portion of the semiconductor structure; and
filling the trenches in the first and second portions of the semiconductor structure with a gate region.

### Claim 2 (depends on 1)

The method of claim 1 wherein the PDSOI layer has a thickness of 5 to 200 nm.

### Claim 3 (depends on 2)

The method of claim 2 wherein the top semiconductor layer in the second portion is thicker than the top semiconductor layer in the first portion.

### Claim 4 (depends on 1)

The method of claim 1 wherein between removing the plurality of patterned hard masks and removing each layer of sacrificial material, further comprising forming a spacer within the trenches of the first and second portions of the semiconductor structure.

### Claim 5 (depends on 1)

The method of claim 1 wherein said removing each layer of sacrificial material is performed by chemically utilizing an etchant that exploits the lower oxidation potential of the layers of sacrificial material compared to the layers of semiconductor material.

### Claim 6 (depends on 1)

The method of claim 1 wherein said removing each layer of sacrificial material is performed by utilizing a plasma etching process.

### Claim 7 (depends on 1)

The method of claim 1 wherein said removing each layer of sacrificial material is performed using a wet or dry oxidation process.

### Claim 8 (depends on 1)

The method of claim 1 wherein each semiconductor nanowire has a pitch of less than 200 nm and a width of less than 40 nm.

### Claim 9 (depends on 1)

The method of claim 1 wherein a nanowire mesh device is formed in the first portion of the semiconductor structure and a PDSOI device is formed in a second portion of the semiconductor structure.

### Claim 10 (depends on 1)

The method of claim 1 wherein a plurality of nanowire mesh devices are formed in the first portion of the semiconductor structure and a plurality of PDSOI devices are formed in a second portion of the semiconductor structure.

### Claim 11 (depends on 10)

The method of claim 10 wherein the semiconductor structure is an integrated circuit.

### Claim 12

A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising:
a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one partially depleted semiconductor on insulator (PDSOI) device;
the at least one nanowire mesh device comprising:
a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
the at least one PDSOI device comprising:
a partially depleted semiconductor layer on the substrate; and a gate region including a gate dielectric and a gate conductor over at least a portion of the partially depleted semiconductor layer.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12 wherein each of said semiconductor nanowires has a pitch of less than 200 nm and a width of less than 40 nm.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12 wherein each of said semiconductor nanowires comprises a Si-containing semiconductor material.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12 further comprising a spacer located adjacent to the gate region in the first and second portions of the SOI substrate.

### Claim 16 (depends on 12)

The semiconductor structure of claim 12 wherein the first portion of the SOI substrate containing a plurality of nanowire mesh devices and the second portion of the SOI substrate containing a plurality of PDSOI devices.

### Claim 17 (depends on 12)

The semiconductor structure of claim 12 wherein the SOI substrate comprises a semiconductor base, a buried insulating layer and a top semiconductor layer such that a thickness of the top semiconductor layer in the second portion is greater than the top semiconductor layer in the first portion.

### Claim 18

An integrated circuit comprising:
an semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate, the semiconductor hybrid structure comprising:
first portions of the SOI substrate containing a plurality of nanowire mesh devices and second portions of the SOI substrate containing a plurality of partially depleted semiconductor on insulator (PDSOI) devices;
each of the plurality of nanowire mesh devices comprising:
a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
each of the plurality of PDSOI devices comprising:
a partially depleted semiconductor layer on the substrate; and a gate region including a gate dielectric and a gate conductor over at least a portion of the partially depleted semiconductor layer.

### Claim 19 (depends on 18)

The integrated circuit of claim 18 wherein the SOI substrate comprises a semiconductor base, a buried insulating layer and a top semiconductor layer such that a thickness of the top semiconductor layer in the second portions is greater than a thickness of the top semiconductor layer in the first portions.

### Claim 20 (depends on 18)

The integrated circuit of claim 18 wherein each of said semiconductor nanowires has a pitch of less than 200 nm and a width of less than 40 nm.