# US 2013/0153994 A1 · Trench type power transistor device with super junction and manufacturing method thereof

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- Number: US 2013/0153994 A1
- Document ID: US20130153994A1
- Status: Published application
- Kind: A1
- Application number: 13/556,166
- Filed: 2012-07-23
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Anpec Electronics Corporation
- Inventors: Yung-Fa Lin; Shou-Yi Hsu; Meng-Wei Wu; Chia-Hao Chang
- Web page: https://patentgrep.com/patent/US20130153994A1

## CPC

- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/159: {Shapes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.

## Claims

### Claim 1

A manufacturing method of a trench type power transistor device with a super junction, comprising:
providing a substrate of a first conductivity type;
forming an epitaxial layer of a second conductivity type different from said first conductivity type on said substrate;
forming at least one through hole penetrating through said epitaxial layer in said epitaxial layer;
forming two doped drain regions of said first conductivity type in said epitaxial layer respectively at both sides of said through hole, wherein said doped drain regions extend from the upper surface of said epitaxial layer to be in contact with said substrate;
filling an insulating layer into said through hole, wherein the upper surface of said insulating layer is lower than the upper surface of said epitaxial layer;
forming a doped channel region of said second conductivity type respectively in said epitaxial layer at each said side of said through hole on said insulating layer;
forming a gate structure in said through hole on said insulating layer; and
forming a doped source region of said first conductivity type respectively on each said doped channel region.

### Claim 2 (depends on 1)

The manufacturing method of a trench type power transistor device with a super junction according to claim 1, wherein the manufacturing method between the step of forming said epitaxial layer and the step of forming said through hole further comprises:
forming a first hard mask layer and a second hard mask layer sequentially on said epitaxial layer; and
patterning said second hard mask layer and said first hard mask layer to expose said epitaxial layer.

### Claim 3 (depends on 2)

The manufacturing method of a trench type power transistor device with a super junction according to claim 2, wherein the manufacturing method between the step of forming said epitaxial layer and the step of forming said first hard mask further comprises:
forming a liner layer on said epitaxial layer; and
forming a well region of said second conductivity type in said epitaxial layer.

### Claim 4 (depends on 2)

The manufacturing method of a trench type power transistor device with a super junction according to claim 2, wherein the step of forming said insulating layer comprises:
forming an insulating material layer on said second hard mask layer, wherein said insulating material layer fills up said through hole;
performing a polishing process to remove said insulating material layer outside said through hole and said second hard mask layer; and
performing an etching process to remove a part of said insulating material layer in said through hole, so as to form said insulating layer.

### Claim 5 (depends on 1)

The manufacturing method of a trench type power transistor device with a super junction according to claim 1, wherein the step of forming said doped drain regions comprises a tilt-angle ion implantation process or a vapor phase doping process.

### Claim 6 (depends on 1)

The manufacturing method of a trench type power transistor device with a super junction according to claim 1, wherein between the step of forming said insulating layer and the step of forming said doped channel regions, the manufacturing method further comprises:
forming two oxide layers respectively on the two sidewalls of said through hole on said insulating layer, wherein a part of each said doped drain region close to said through hole is transformed to a part of each said oxide layer; and
performing a wet etching process to remove said oxide layers.

### Claim 7 (depends on 1)

The manufacturing method of a trench type power transistor device with a super junction according to claim 1, wherein the step of forming said doped channel regions comprises a tilt-angle ion implantation process or a vapor phase doping process.

### Claim 8 (depends on 1)

The manufacturing method of a trench type power transistor device with a super junction according to claim 1, wherein the manufacturing method between the step of forming said doped channel regions and the step of forming said gate structure further comprises removing said first hard mask layer and said liner layer.

### Claim 9

A manufacturing method of a trench type power transistor device with a super junction, comprising:
providing a substrate of first conductivity type;
forming a first epitaxial layer of a second conductivity type different from said first conductivity type on said substrate;
forming at least one first through hole extending through said first epitaxial layer in said first epitaxial layer;
forming two doped drain regions of said first conductivity type respectively in said first epitaxial layer at both sides of said first through hole, wherein said doped drain regions extend from the upper surface of said first epitaxial layer to be in contact with said substrate;
filling up said first through hole with an insulating layer;
forming a second epitaxial layer of said second conductivity type on said first epitaxial layer and said insulating layer;
forming at least one second through hole in said second epitaxial layer to expose said insulating layer;
forming a gate structure in said second through hole; and
forming two doped source regions of said first conductivity type in said second epitaxial layer at both sides of said second through hole.

### Claim 10 (depends on 9)

The manufacturing method of a trench type power transistor device with a super junction according to claim 9, wherein the manufacturing method between the step of forming said first epitaxial layer and the step of forming said first through hole further comprises:
forming a hard mask layer on said first epitaxial layer; and
patterning said hard mask layer to expose said first epitaxial layer.

### Claim 11 (depends on 10)

The manufacturing method of a trench type power transistor device with a super junction according to claim 10, wherein the step of forming said insulating layer comprises:
forming an insulating material layer on said hard mask layer, wherein said insulating material layer fills up said first through hole; and
removing said insulating material layer outside said first through hole and said hard mask layer, so as to form said insulating layer in said first through hole.

### Claim 12 (depends on 9)

The manufacturing method of a trench type power transistor device with a super junction according to claim 9, wherein the step of forming said doped drain regions comprises a tilt-angle ion implantation process or a vapor phase doping process.

### Claim 13 (depends on 9)

The manufacturing method of a trench type power transistor device with a super junction according to claim 9, wherein the manufacturing method between the step of forming said second through hole and the step of forming said gate structure further comprises forming a doped channel region in said second epitaxial layer respectively at each said side of said second through hole.

### Claim 14 (depends on 13)

The manufacturing method of a trench type power transistor device with a super junction according to claim 13, wherein the step of forming said doped channel regions comprises a tilt-angle ion implantation process and a vapor phase doping process.

### Claim 15

A trench type power transistor device with a super junction, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type different from said first conductivity type, wherein said first epitaxial layer is disposed on said substrate and has at least one through hole;
at least two doped drain regions of said first conductivity type which are disposed in said first epitaxial layer at both sides of said through hole and contact said substrate;
an insulating layer disposed in said through hole and having an upper surface lower than the upper surface of said first epitaxial layer;
at least two doped channel regions of said second conductivity type region which are disposed respectively in said first epitaxial layer on said doped drain regions and respectively contact said doped drain regions;
a gate structure disposed in said through hole on said insulating layer; and
at least two doped source regions of said first conductivity type disposed in said first epitaxial layer respectively at said sides of said through hole and respectively being in contact with said doped channel regions.

### Claim 16 (depends on 15)

The trench type power transistor device with a super junction according to claim 15, further comprising a well region of said second conductivity disposed in said first epitaxial layer on said insulating layer, wherein said doped channel regions and said doped source regions are disposed in said well region.

### Claim 17 (depends on 15)

The trench type power transistor device with a super junction according to claim 15, wherein said gate structure comprises a gate conductive layer and a gate insulator layer, wherein said gate insulator layer is disposed between said gate conductive layer and said first epitaxial layer.

### Claim 18

A trench type power transistor device with a super junction, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type different from said first conductivity type, wherein said first epitaxial layer is disposed on said substrate and has at least one first through hole;
at least two doped drain regions of said first conductivity type which are disposed in said first epitaxial layer at both sides of said first through hole and extend from the upper surface of said first epitaxial layer to be in contact with said substrate;
an insulating layer filling up said first through hole;
a second epitaxial layer of said second conductivity type which is disposed on said first epitaxial layer and contacts said doped drain regions, wherein said second epitaxial layer has at least one second through hole disposed on said insulating layer;
a gate structure disposed in said second through hole on said insulating layer; and
at least two doped source regions of said first conductivity type disposed respectively in said second epitaxial layer at both sides of said second through hole.

### Claim 19 (depends on 18)

The trench type power transistor device with a super junction according to claim 18, wherein said gate structure comprises a gate conductive layer and a gate insulator layer, wherein said gate insulator layer is disposed between said gate conductive layer and said second epitaxial layer.

### Claim 20 (depends on 18)

The trench type power transistor device with a super junction according to claim 18, further comprising at least two doped channel regions of said second conductivity type disposed respectively in said second epitaxial layer between said doped drain regions and said doped source regions.