# US 2013/0153992 A1 · Electronic device including a tapered trench and a conductive structure therein and a process of forming the same

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- Number: US 2013/0153992 A1
- Document ID: US20130153992A1
- Status: Published application
- Kind: A1
- Application number: 13/327,422
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Semicondcutor Components Industries, LLC
- Inventors: Gary H. Loechelt
- Web page: https://patentgrep.com/patent/US20130153992A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 64/01: Manufacture or treatment
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/111: {Field plates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench.

## Claims

### Claim 1

An electronic device comprising:
a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;
a trench extending into the semiconductor layer and having a tapered shape including a relatively wider portion adjacent to the primary surface and a relatively narrower portion farther from the primary surface as compared to the relatively wider portion, wherein, from a cross-sectional view, the relatively narrower portion is defined by a substantially planar sidewall that lies along a second plane that intersects the first plane at an angle of greater than approximately 70°; and
a doped semiconductor region that lies adjacent to a sidewall of the trench having the tapered shape, wherein the doped semiconductor region extends to the narrower portion and has a dopant concentration greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface.

### Claim 2 (depends on 1)

The electronic device of claim 1, further comprising a conductive structure disposed within the trench below the doped semiconductor region.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein the doped semiconductor region is electrically connected to the conductive structure.

### Claim 4 (depends on 3)

The electronic device of claim 3, further comprising an underlying doped region, wherein:
the semiconductor layer is disposed over the underlying doped region; and
the conductive structure is electrically connected to the underlying doped region.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein:
the electronic device comprises a transistor structure; and
the doped semiconductor region is part of a drain region of the transistor structure.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the doped semiconductor region has a dopant concentration in a range of approximately 5×1016 atoms/cm3 to approximately 5×1018 atoms/cm3.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the tapered shape comprises a funnel shape.

### Claim 8

An electronic device comprising:
a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane; and
a trench having a first portion, a second portion, and a third portion, wherein:
the first, second, and third portions are disposed within the semiconductor layer;
the first and third portions are tapered; and
from a cross-sectional view, the second portion is defined by a sidewall that lies along a second plane that intersects the first plane at an angle of greater than approximately 70°.

### Claim 9 (depends on 8)

The electronic device of claim 8, further comprising a doped semiconductor region disposed along the first, second, and third portions of the trench, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface.

### Claim 10 (depends on 9)

The electronic device of claim 9, further comprising a conductive structure, wherein:
the trench has a fourth portion disposed within the semiconductor layer at an elevation below the first, second, and third portions of the trench; and
the conductive structure is disposed within the fourth portion of the trench.

### Claim 11 (depends on 10)

The electronic device of claim 10, wherein the fourth portion of the trench has a substantially vertical sidewall.

### Claim 12 (depends on 9)

The electronic device of claim 9, further comprising:
a first insulating layer disposed along the first portion of the trench;
a second insulating layer disposed along a second portion of the trench, wherein the second insulating layer is thicker than the first insulating layer; and
a conductive electrode, wherein:
the first insulating layer is disposed between the first portion of the trench and the conductive electrode; and
the second insulating layer is disposed between the second portion of the trench and the conductive electrode.

### Claim 13

An electronic device comprising:
a semiconductor layer overlying a substrate and having a primary surface, wherein the primary surface generally lies substantially along a plane;
a trench having a tapered shape;
a conductive structure within a relatively narrower portion of the trench; and
a conductive electrode within a relatively wider portion of the trench, wherein the conductive electrode and the conductive structure are electrically insulated from each other.

### Claim 14 (depends on 13)

The electronic device of claim 13, wherein the conductive electrode extends into the trench such that a lowest elevation of the conductive electrode is at least approximately 0.3 microns below an elevation of the plane corresponding to the primary surface.

### Claim 15 (depends on 13)

The electronic device of claim 13, further comprising:
a doped semiconductor region adjacent to the tapered portion, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface; and
an insulating layer disposed between the doped semiconductor region and the conductive electrode, wherein:
the insulating layer has a first portion and a second portion; and
as compared to the second portion of the insulating layer, the first portion of the insulating layer is thinner and disposed closer to the primary surface.

### Claim 16 (depends on 13)

The electronic device of claim 13, wherein the tapered shape comprises a funnel shape.

### Claim 17

A process of forming an electronic device comprising:
providing a semiconductor layer overlying a substrate and having a primary surface;
patterning the semiconductor layer to define a trench having a tapered portion;
forming a first insulating layer within the tapered portion;
forming a sacrificial plug within the tapered portion;
removing a first portion of the first insulating layer from the tapered portion, wherein the sacrificial plug substantially protects a second portion of the first insulating layer when removing the first portion of the first insulating layer;
removing the sacrificial plug; and
forming a conductive electrode at a location from which the sacrificial plug was removed.

### Claim 18 (depends on 17)

The process of claim 17, further comprising forming a second insulating layer after removing the portion of the first insulating layer, wherein the second insulating layer is thinner than the first insulating layer.

### Claim 19 (depends on 17)

The process of claim 17, further comprising forming a conductive structure, wherein:
patterning the semiconductor layer comprises forming another portion of the trench, wherein the other portion has substantially vertical sidewalls and is disposed below the tapered portion; and
forming the conductive structure comprises forming the conductive structure within the other portion of the trench before forming the first insulating layer.

### Claim 20 (depends on 19)

The process of claim 19, further comprising forming a doped semiconductor region adjacent to the tapered portion, wherein:
forming the doped semiconductor region is performed after forming the conductive structure and before forming the first insulating layer; and
a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface

### Claim 21 (depends on 18)

The process of claim 18, wherein the first and second insulating layers have substantially a same composition.