# US 2013/0153987 A1 · Electronic device comprising a conductive structure and an insulating layer within a trench and a process of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0153987 A1 - Document ID: US20130153987A1 - Status: Published application - Kind: A1 - Application number: 13/327,361 - Filed: 2011-12-15 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Semiconductor Components Industries, LLC - Inventors: Prasad Venkatraman; Gordon M. Grivna; Gary H. Loechelt - Web page: https://patentgrep.com/patent/US20130153987A1 ## CPC - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} - H10D 30/0285: {using formation of insulating sidewall spacers} - H10D 30/0287: {using recessing of the source electrodes} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 64/0133: {at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench. ## Claims ### Claim 1 An electronic device comprising: a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a first trench extends through at least approximately 50% of the thickness of semiconductor layer to a first depth; a first conductive structure within the first trench, wherein the first conductive structure extends at least approximately 50% of the first depth of the first trench; a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the first conductive structure; and a first insulating layer disposed between the vertically-oriented doped region and the first conductive structure. ### Claim 2 (depends on 1) The electronic device of claim 1, wherein: other than rounding at a bottom of the first trench, the first trench has a substantially uniform width; and the vertically-oriented doped region is immediately adjacent to the first trench. ### Claim 3 (depends on 1) The electronic device of claim 1, wherein the vertically-oriented doped region extends to a second depth that is at least approximately 20% of thickness of the semiconductor layer. ### Claim 4 (depends on 1) The electronic device of claim 1, further comprising a channel region having a corresponding channel length that extends in a direction substantially parallel to the primary surface of the semiconductor layer. ### Claim 5 (depends on 1) The electronic device of claim 1, further comprising: a second trench that extends through at least approximately 50% of the thickness of semiconductor layer, wherein the second trench spaced-apart from the first trench; a second conductive structure within the second trench, wherein the second conductive structure extends through at least approximately 50% of the thickness semiconductor layer; a source region outside of and adjacent to the second trench, wherein the source region is spaced apart from the vertically oriented doped region by a channel region; and a second insulating layer disposed between the source region and the second conductive structure. ### Claim 6 (depends on 5) The electronic device of claim 5, wherein the second conductive structure has a substantially uniform width, and the first conductive structure has a first portion with a first width and a second portion with a second width different from the first width. ### Claim 7 (depends on 5) The electronic device of claim 5, wherein: the first insulating layer is significantly thicker along a bottom of the first trench compared to any other portion of the first insulating layer along a sidewall of the first trench; the second insulating layer is significantly thicker along a bottom of the second trench compared to any other portion of the second insulating layer along a sidewall of the second trench; or any combination thereof ### Claim 8 (depends on 1) The electronic device of claim 1, further comprising an underlying doped region spaced apart from the primary surface and underlying the channel region, wherein the underlying doped region is part of a drain region, is coupled to the vertically-oriented doped region, and is electrically insulated from the first conductive structure. ### Claim 9 (depends on 8) The electronic device of claim 8, further comprising: a body region that includes a channel region; and a superjunction extending below the body region towards the underlying doped region. ### Claim 10 (depends on 1) The electronic device of claim 1, wherein: the first conductive structure includes a first portion and a second portion disposed over the first portion; the first portion is farther from the primary surface of the semiconductor layer as compared to the second portion; and the first portion is narrower and deeper than the second portion. ### Claim 11 (depends on 1) The electronic device of claim 1, further comprising a gate member that does not directly overlie the first trench. ### Claim 12 A process of forming an electronic device comprising: forming a semiconductor layer over a substrate, wherein the semiconductor layer has a primary surface and a thickness; patterning the semiconductor layer to define a first trench extending through at least approximately 50% of the thickness of the semiconductor layer; forming a first insulating layer within the first trench; forming a vertically-oriented doped region within the semiconductor layer and extending from near the primary surface towards the substrate, wherein the vertically-oriented doped region is formed after patterning the semiconductor layer to define the first trench; and forming a first conductive structure within the first trench, wherein the first insulating layer is disposed between the semiconductor layer and the first conductive structure. ### Claim 13 (depends on 12) The process of claim 12, wherein patterning the semiconductor layer is performed such that, other than rounding at a bottom of the first trench, the first trench has a substantially uniform width. ### Claim 14 (depends on 12) The process of claim 12, wherein forming the first conductive structure comprises: filling a first portion of the first trench with a first conductive fill material; removing a portion, but not all, of the first insulating layer within the first trench after filling the first portion of the trench with the first conductive fill material; and filling a second portion of the trench with a second conductive fill material after removing a portion, but not all, of the first insulating layer. ### Claim 15 (depends on 12) The process of claim 12, wherein forming the vertically-oriented doped region and forming the first conductive structure comprise: filling the first trench with a first conductive fill material; removing a portion, but not all, of the first conductive fill material; forming the vertically-oriented doped region after removing the portion of the first conductive fill material; and filling a second portion of the first trench with a second conductive fill material after forming the vertically-oriented doped region. ### Claim 16 (depends on 12) The process of claim 12, further comprising: forming a gate electrode layer; and anisotropically etching the gate electrode layer to form a gate member, wherein anisotropically etching removes substantially an entire thickness of the gate electrode layer from over a portion of the first conductive structure. ### Claim 17 (depends on 16) The process of claim 16, further comprising forming a patterned resist layer over the gate electrode layer, wherein anisotropically etching is performed while the resist layer overlies the gate electrode layer. ### Claim 18 (depends on 12) The process of claim 12, further comprising: patterning the semiconductor layer to define a second trench that extends through at least approximately 50% of the thickness of semiconductor layer, wherein the second trench is spaced-apart from the first trench; forming a second insulating layer within the second trench; forming a second conductive structure within the second trench after forming the second insulating layer; and forming a source region outside of and adjacent to the second trench, wherein the source region is spaced apart from the vertically-oriented doped region by a channel region. ### Claim 19 (depends on 18) The process of claim 18, wherein: forming the first insulating layer comprises forming a first insulating film within the first and second trenches, and forming a second insulating film within the first and second trenches after forming the first insulating film; and removing a portion, but not all, of the first insulating layer comprises selectively etching the second insulating film in preference to the first insulating film within the first trench, and not etching a significant amount of the second insulating film within the second trench. ### Claim 20 (depends on 18) The process of claim 18, wherein forming the vertically-oriented doped region, forming the first conductive structure, and forming the second conductive structure comprise: filling the first and second trenches with a first conductive fill material; removing a portion, but not all, of the first conductive fill material from within the first trench, and not removing a significant portion of the first conductive fill material from the second trench; forming the vertically-oriented doped region immediately adjacent to a sidewall of the first trench after removing the portion of the first conductive fill material, wherein no vertically-oriented doped region is formed immediately adjacent to a sidewall of the second trench; and filling a second portion of the first trench with a second conductive fill material after forming the vertically-oriented doped region.