# US 2013/0153984 A1 · Semiconductor Constructions, NAND Unit Cells, Methods of Forming Semiconductor Constructions, and Methods of Forming NAND Unit Cells

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- Number: US 2013/0153984 A1
- Document ID: US20130153984A1
- Status: Published application
- Kind: A1
- Application number: 13/765,643
- Filed: 2013-02-12
- Published: 2013-06-20
- Earliest claimed: 2008-01-15
- Assignees: Micron Technology, Inc.
- Inventors: D.V. Nirmal Ramaswamy
- Web page: https://patentgrep.com/patent/US20130153984A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 30/697: {having trapping at multiple separated sites, e.g. multi-particles trapping sites}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

## Claims

### Claim at position 1

1-16. (canceled)

### Claim 17

A NAND unit cell, comprising:
a first vertical column comprising alternating control gate structures and insulative material structures;
second and third vertical columns on opposing sides of the first vertical column from one another, the second and third vertical columns comprising semiconductor material containing alternating n-type doped regions and p-type doped regions; the n-type doped regions of the second vertical column being horizontally aligned with the n-type doped regions of the third vertical column, and the p-type doped regions of the second vertical column being horizontally aligned with the p-type doped regions of the third vertical column; the control gate structures being horizontally aligned with either the n-type doped regions or the p-type doped regions;
vertically-extending layers of tunnel dielectric, charge-storage material, and charge-blocking material between the first column and each of the second and third columns; and
wherein at least one of the control gate structures, together with n-type and p-type doped regions of the second and third vertical columns, is incorporated into a string device of the NAND unit cell.

### Claim 18 (depends on 17)

The NAND unit cell of claim 17 wherein the first vertical column is vertically between a pair of selecting devices of the NAND unit cell.

### Claim 19 (depends on 17)

The NAND unit cell of claim 17 wherein the first vertical column comprises a bottom control gate structure, a top control gate structure, and at least one intermediate control gate structure between the bottom control gate structure and the top control gate structure; the top and bottom control gate structures, together with n-type and p-type doped regions of the second and third vertical columns, being incorporated into selecting devices of the NAND unit cell; and the at least one intermediate control gate structure, together with n-type and p-type doped regions of the second and third vertical columns, being incorporated into at least one string device of the NAND unit cell.

### Claim 20 (depends on 17)

The NAND unit cell of claim 17 wherein the second and third vertical columns consist of doped monocrystalline silicon.

### Claim 21 (depends on 17)

The NAND unit cell of claim 17 wherein the control gate structures are horizontally aligned with the p-type doped regions.

### Claim 22

A semiconductor construction, comprising:
a semiconductor base;
a plurality of pillars extending upwardly from the base, the pillars comprising alternating n-type doped semiconductor material and p-type doped semiconductor material; a pair of the pillars being adjacent one another, the adjacent pillars being a first pillar and a second pillar;
tunnel dielectric between the adjacent pillars; the tunnel dielectric including a first region along and directly against the p-type and n-type doped semiconductor material of the first pillar, and including a second region along and directly against the p-type and n-type doped semiconductor material of the second pillar;
charge-storage material along the tunnel dielectric; the charge-storage material including a first region along and directly against the first region of the tunnel dielectric, and including a second region along and directly against the second region of the tunnel dielectric;
charge-blocking material along the charge-storage material; the charge-blocking material including a first region along and directly against the first region of the charge-storage material, and including a second region along and directly against the second region of the charge-storage material;
a plurality of control gate structures that are horizontally spaced from one another; the control gate structures being laterally between the adjacent pillars, and laterally between the first and second regions of the charge-blocking material; and
insulative spacers within spaces between the horizontally-spaced control gate structures.

### Claim 23 (depends on 22)

The semiconductor construction of claim 22 wherein the control gate structures are comprised by electrically conductive lines that extend along a horizontal direction;
further comprising electrically insulative dividers between some of the pillars of the plurality of pillars, with said electrically insulative dividers being vertical columns that extend along an entire vertical periphery of the pillars; and wherein the electrically conductive lines are between adjacent electrically insulative dividers.

### Claim 24 (depends on 22)

The semiconductor construction of claim 22 wherein the horizontally-spaced control gate structures include a bottom control gate structure, a top control gate structure, and at least one intermediate control gate structure between the bottom control gate structure and the top control gate structure; the top and bottom control gate structures being incorporated into selecting devices of a NAND unit cell, and the at least one intermediate control gate structure being incorporated into at least one string device of the NAND unit cell.

### Claim 25 (depends on 22)

The semiconductor construction of claim 22 wherein the horizontally-spaced control gate structures are a first set of horizontally-spaced control gate structures, and further comprising a second set of horizontally-spaced control gate structures on an opposing side of one of the adjacent pillars from said first set of horizontally-spaced control gate structures; the alternating p-type doped regions and n-type doped regions of said one of the adjacent pillars forming channel regions and source/drain regions for a first set of flash memory cells comprising the first set of horizontally-spaced control gate structures, and for a second set of flash memory cells comprising the second set of horizontally-spaced control gate structures.

### Claim 26

A NAND unit cell, comprising:
a first vertical column comprising alternating control gate structures and insulative material structures;
second and third vertical columns on opposing sides of the first vertical column from one another, the second and third vertical columns comprising alternating n-type doped regions and p-type doped regions; at least four of the n-type doped regions alternating with at least three of the p-type doped regions; the n-type doped regions of the second vertical column being horizontally aligned with the n-type doped regions of the third vertical column, and the p-type doped regions of the second vertical column being horizontally aligned with the p-type doped regions of the third vertical column; the control gate structures being horizontally aligned with either the n-type doped regions or the p-type doped regions;
tunnel dielectric, charge-storage material, and charge-blocking material between the first column and each of the second and third columns; the tunnel dielectric being configured as an upwardly-opening container; the control gate structures and insulative material structures being within said container; and
wherein at least some of the control gate structures, together with n-type and p-type doped regions of the second and third vertical columns, are incorporated into string devices of the NAND unit cell.