# US 2013/0153983 A1 · 3-d nonvolatile memory device, memory system including the 3-d nonvolatile memory device, and method of manufacturing the 3-d nonvolatile memory device

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- Number: US 2013/0153983 A1
- Document ID: US20130153983A1
- Status: Published application
- Kind: A1
- Application number: 13/601,641
- Filed: 2012-08-31
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: SK hynix Inc.
- Inventors: Yoo Nam JEON
- Web page: https://patentgrep.com/patent/US20130153983A1

## CPC

- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A three dimensional (3-D) nonvolatile memory device includes a first pipe gate layer, a second pipe gate disposed over the first pipe gate layer, word lines formed over the second pipe gate layer, memory channel layers configured to penetrate the word lines, a pipe channel layer formed in the first pipe gate layer, where the pipe channel layer is to come in contact with the bottom surface of the second pipe gate layer and couple the lower ends of the memory channel layers, a memory layer configured to surround the pipe channel layer and the memory channel layers, and a first gate insulating layer interposed between the first pipe gate layer and the memory layer.

## Claims

### Claim 1

A three dimensional (3-D) nonvolatile memory device, comprising:
a first pipe gate layer;
a second pipe gate disposed over the first pipe gate layer;
word lines formed over the second pipe gate layer;
memory channel layers configured to penetrate the word lines;
a pipe channel layer formed in the first pipe gate layer, where the pipe channel layer is to come in contact with a bottom surface of the second pipe gate layer and couple lower ends of the memory channel layers;
a memory layer configured to surround the pipe channel layer and the memory channel layers; and
a first gate insulating layer interposed between the first pipe gate layer and the memory layer.

### Claim 2 (depends on 1)

The 3-D nonvolatile memory device of claim 1, further comprising:
a second gate insulating layer interposed between the second pipe gate layer and the memory layer.

### Claim 3 (depends on 1)

The 3-D nonvolatile memory device of claim 1, wherein the first gate insulating layer includes an oxide layer and a nitride layer.

### Claim 4 (depends on 1)

The 3-D nonvolatile memory device of claim 1, wherein the memory layer comprises:
a tunnel insulating layer configured to surround the memory channel layer,
a charge trap layer configured to surround the tunnel insulating layer, and
a charge blocking layer configured to surround the charge trap layer.

### Claim 5 (depends on 4)

The 3-D nonvolatile memory device of claim 4, wherein a region of the charge blocking layer interposed between each of the word lines and the charge trap layer is thicker than other regions of the charge blocking layer.

### Claim 6

A memory system, comprising:
a 3-D nonvolatile memory device configured to comprise a first pipe gate layer,
a second pipe gate layer disposed over the first pipe gate layer,
word lines stacked over the second pipe gate layer,
memory channel layers configured to penetrate the word lines, a pipe channel layer formed in the first pipe gate layer, where the pipe channel layer is to come in contact with a bottom surface of the second pipe gate and couple lower ends of the memory channel layers,
a memory layer configured to surround the pipe channel layer and the memory channel layers, and
a first gate insulating layer interposed between the first pipe gate layer and the memory layer; and
a memory controller configured to control the nonvolatile memory device.

### Claim 7 (depends on 6)

The memory system of claim 6, further comprising:
a second gate insulating layer interposed between the second pipe gate layer and the memory layer.

### Claim 8 (depends on 6)

The memory system of claim 6, wherein the memory layer comprises:
a tunnel insulating layer configured to surround the memory channel layer;
a charge trap layer configured to surround the tunnel insulating layer; and
a charge blocking layer configured to surround the charge trap layer.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein a region of the charge blocking layer interposed between each of the word lines and the charge trap layer, is thicker than other regions of the charge blocking layer.

### Claim 10

A method of manufacturing a three dimensional (3-D) nonvolatile memory device, the method comprising:
forming a first trench by etching a conductive layer for a first pipe gate layer ;
forming a first gate insulating layer on an inside surface of the first trench;
filling the first trench, on which the first gate insulating layer has been formed, with a sacrificial layer;
forming a conductive layer for a second pipe gate layer on the conductive layer for the first pipe gate layer in which the sacrificial layer has been filled ;
alternately forming first material layers and second material layers over the second pipe gate layer;
forming second trenches coupled to the first trench by etching the first material layers, the second material layers, and the conductive layer of the second pipe gate layer;
removing the sacrificial layer;
forming a memory layer on inside surfaces of the first trench and of the second trenches; and
forming a channel layer over the memory layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a second gate insulating layer by oxidizing the conductive layer for the second pipe gate layer, that is exposed via the first trench and the second trenches, after the sacrificial layer has been removed.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first gate insulating layer includes an oxide layer and a nitride layer.

### Claim 13 (depends on 10)

The method of claim 10, wherein forming the memory layer comprises:
forming a first charge blocking layer on the insides of the first trench and the second trenches;
forming a charge trap layer on the first charge blocking layer; and
forming a tunnel insulating layer on the charge trap layer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming at least one slit by etching the first material layers and the second material layers, after forming the channel layer;
removing the first material layers exposed to inner walls of the slit;
oxidizing the first charge blocking layer exposed by removing the first material layers; and
filling regions from which the first material layers have been removed with a conductive layer.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
forming at least one slit by etching the first material layers and the second material layers, after forming the channel layer;
removing the first material layers exposed by the slit;
etching the first charge blocking layer, of the memory layer, exposed by removing the first material layers;
forming a second charge blocking layer on the charge trap layer, which is exposed by the etching of the first charge blocking layer; and
filling regions from which the first material layers have been removed with a conductive layer.