# US 2013/0153979 A1 · Three-dimensional non-volatile memory device, memory system and method of manufacturing the same

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- Number: US 2013/0153979 A1
- Document ID: US20130153979A1
- Status: Published application
- Kind: A1
- Application number: 13/605,982
- Filed: 2012-09-06
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Inventors: Yoo Hyun NOH; Jong Moo Choi; Young Soo Ahn
- Web page: https://patentgrep.com/patent/US20130153979A1

## CPC

- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10P 30/22: using masks
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.

## Claims

### Claim 1

A three-dimensional (3-D) non-volatile memory device, comprising:
channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively;
vertical gates located and spaced from each other between the channel structures; and
a well pickup line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.

### Claim 2 (depends on 1)

The 3-D non-volatile memory device of claim 1, further comprising:
word lines coupled to the vertical gates and extending in the second direction crossing the channel structures; and
a memory layer interposed between the channel structures and the vertical gates, and between the channel structures and each of the word lines.

### Claim 3 (depends on 1)

The 3-D non-volatile memory device of claim 1, further comprising junctions formed in the channel layers exposed between the vertical gates.

### Claim 4 (depends on 3)

The 3-D non-volatile memory device of claim 3, wherein the channel layers include P type impurities at a low concentration, the junctions include N type impurities and the well regions include the P type impurities at a high concentration.

### Claim 5 (depends on 1)

The 3-D non-volatile memory device of claim 1, further comprising:
source regions formed in each of the channel layers; and
a source line contacting on the source regions of the channel layers and extending in the second direction crossing the channel structures.

### Claim 6 (depends on 5)

The 3-D non-volatile memory device of claim 5, wherein the channel layers include P type impurities at a low concentration, the source regions include N type impurities and the well regions include the P type impurities at a high concentration.

### Claim 7

A memory system, comprising:
a three-dimensional (3-D) non-volatile memory device including channel structures each having channel layers that are stacked over a substrate and includes respective well regions, vertical gates located and spaced from each other between the channel structures, and a well pickup line contacting on the well regions of the channel layers and extending in a direction crossing the channel structures; and
a memory controller configured to control the 3-D non-volatile memory device.

### Claim 8 (depends on 7)

The memory system of claim 7, further comprising junctions formed in the channel layers exposed between the vertical gates.

### Claim 9 (depends on 7)

The memory system of claim 7, further comprising:
source regions formed in each of the channel layers; and
a source line contacting on the source regions of the channel layers and extending in the direction crossing the channel structures.

### Claim 10

A method of manufacturing a three-dimensional (3-D) non-volatile memory device, the method comprising:
forming channel structures each including channel layers and interlayer insulating layers stacked alternately over a substrate, wherein the channel layers include well regions, respectively;
forming vertical gates spaced from each other between the channel structures; and
forming a well pickup line contacting on the well regions of the channel layers and extending in a direction crossing the channel structures.

### Claim 11 (depends on 10)

The method of claim 10, wherein the forming of the channel structures comprises:
alternately forming the interlayer insulating layers and the channel layers over the substrate; and
etching the interlayer insulating layers and the channel layers to form the channel structures extending in parallel along one direction.

### Claim 12 (depends on 11)

The method of claim 11, wherein the forming of the interlayer insulating layers and the channel layers comprises:
doping a portion of each of the channel layers with impurities to form a well region after forming the each of the channel layers.

### Claim 13 (depends on 11)

The method of claim 11, wherein the forming of the channel structures further comprises:
forming a mask pattern exposing portions of the channel structures corresponding to the well regions of the channel layers; and
forming the well regions in the channel layers by doping the channel layers with impurities by using the mask pattern as a barrier.

### Claim 14 (depends on 10)

The method of claim 10, wherein the forming of the vertical gates comprises:
forming a memory layer over an entire surface of the channel structures;
forming a conductive layer on the memory layer; and
forming the vertical gates and word lines coupled to the vertical gates by etching the conductive layer and the memory layer, wherein the word lines extend in the direction crossing the channel structures.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
forming a mask pattern covering the well regions of the channel layers after the forming of the vertical gates; and
forming junctions in each of the channel layers between the vertical gates and source regions in portions of the channel layers by doping the channel layers exposed between the mask pattern and the vertical gates with impurities.

### Claim 16 (depends on 15)

The method of claim 15, wherein the forming of the junctions and the source regions is performed by using a tilting ion implantation process or a plasma doping process.

### Claim 17 (depends on 15)

The method of claim 15, further comprising forming a source line coupled to the source regions of the channel layers and extending in the direction crossing the channel structures.