# US 2013/0153978 A1 · 3d non-volatile memory device and method of manufacturing the same

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- Number: US 2013/0153978 A1
- Document ID: US20130153978A1
- Status: Published application
- Kind: A1
- Application number: 13/598,528
- Filed: 2012-08-29
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: SK hynix Inc.
- Inventors: Ki Hong LEE; Seung Ho PYI; Seok Min JEON
- Web page: https://patentgrep.com/patent/US20130153978A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

## Claims

### Claim 1

A 3D non-volatile memory device comprising:
a pipe gate;
at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer; and
at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

### Claim 2 (depends on 1)

The 3D non-volatile memory device of claim 1, wherein the first pipe channel layer and the second pipe channel layer are arranged in a staggered manner.

### Claim 3 (depends on 2)

The 3D non-volatile memory device of claim 2, wherein the first pipe channel layer and the second pipe channel layer have different lengths.

### Claim 4 (depends on 2)

The 3D non-volatile memory device of claim 2, further comprising:
at least one first bit line connected to the first channel layer; and
at least one second bit line connected to the second channel layer.

### Claim 5 (depends on 1)

The 3D non-volatile memory device of claim 1, wherein center lines of the first pipe channel layer and second pipe channel layer are positioned in the same line.

### Claim 6 (depends on 5)

The 3D non-volatile memory device of claim 5, wherein a length of the first pipe channel layer is longer than that of the second pipe channel layer.

### Claim 7 (depends on 5)

The 3D non-volatile memory device of claim 5, further comprising:
at least one first drain selection line connected to the first channel layer; and
at least one second drain selection line connected to the second channel layer.

### Claim 8 (depends on 1)

The 3D non-volatile memory device of claim 1, further comprising:
a plurality of source side word lines stacked over the pipe gate, wherein the plurality of source side word lines surround the first source side channel layer and the second source side channel layer; and
a plurality of drain side word lines over the pipe gate, wherein the plurality of drain side word lines surround the first drain side channel layer and the second drain side channel layer.

### Claim 9 (depends on 8)

The 3D non-volatile memory device of claim 8, further comprising:
at least one source selection line stacked over the source side word lines, wherein the source selection line surrounds the first source side channel layer and the second source side channel layer; and
at least one drain selection line stacked over the drain side word lines, wherein the drain selection line surrounds the first drain side channel layer and the second drain side channel layer.

### Claim 10 (depends on 9)

The 3D non-volatile memory device of claim 9, wherein the neighboring source side word lines of neighboring first source side channel layers are connected as a single pattern, and the neighboring source selection lines of the neighboring first source side channel layers are connected as a single pattern.

### Claim 11 (depends on 8)

The 3D non-volatile memory device of claim 8, further comprising:
at least one source selection line stacked over the source side word lines, wherein the source selection line surrounds the first source side channel layer and the second source side channel layer; and
at least one first drain selection line stacked over the drain side word lines, wherein the first drain selection line surrounds the first drain side channel layer; and
at least one second drain selection line stacked over the drain side word lines, wherein the second drain selection line surrounds the second drain side channel layer.

### Claim 12 (depends on 11)

The 3D non-volatile memory device of claim 11, wherein the neighboring source side word lines of neighboring first source side channel layers are connected as a single pattern, and the neighboring source selection lines of the neighboring first source side channel layers are connected as a single pattern.

### Claim 13 (depends on 1)

The 3D non-volatile memory device of claim 1, further comprising a capping layer formed on the pipe gate.

### Claim 14 (depends on 8)

The 3D non-volatile memory device of claim 8, further comprising:
at least one first source selection line stacked over the source side word lines, wherein the first source selection line surrounds the first source side channel layer;
at least one second source selection line stacked over the source side word lines, wherein the second source selection line surrounds the second source side channel layer; and
at least one drain selection line stacked over the drain side word lines, wherein the drain selection line surrounds the first drain side channel layer and the second drain side channel layer.

### Claim 15 (depends on 14)

The 3D non-volatile memory device of claim 14, wherein the neighboring drain side word lines of the neighboring first drain side channel layers are connected as a single pattern, and the neighboring drain selection lines of the neighboring first drain side channel layers are connected as a single pattern.

### Claim 16

A method for manufacturing a 3D non-volatile memory device, the method comprising:
etching a first conductive layer to form first pipe trenches;
forming first sacrificial layers in the first pipe trenches;
forming a second conductive layer on the first conductive layer with the first sacrificial layers formed therein;
etching the second conductive layer to form second pipe trenches;
forming second sacrificial layers in the second pipe trenches; and
alternately forming first material layers and second material layers on the second conductive layer with the second sacrificial layers formed therein.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first and second pipe trenches are formed in a staggered manner.

### Claim 18 (depends on 16)

The method of claim 16, wherein the second pipe trenches are formed to overlap with the respective first pipe trenches and have center lines thereof in the same line.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
forming a capping layer on the second conductive layer, after the forming of the second sacrificial layers.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
etching the first material layers and the second material layers to form a pair of first channel holes connected to each of the first pipe trenches and a pair of second channel holes connected to each of the second pipe trenches, after the alternate forming of the first material layers and the second material layers;
removing the first sacrificial layers and the second sacrificial layers exposed by the pair of first channel holes and the pair of second channel holes to form first channel trenches and second channel trenches;
forming a memory layer along an inner surface of the first channel trenches and the second channel trenches; and
forming first channel layers each including a first pipe channel layer and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and second channel layers each including a second pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer, on the memory layer.

### Claim 21 (depends on 20)

The method of claim 20, further comprising:
etching the first material layers and the second material layers to form at least one first slit positioned between the pair of the second source side channel layer and the second drain side channel layer and at least one third slit positioned between neighboring first drain side channel layers of neighboring first channel layers, among the first channel layers, after the forming of the first channel layers and the second channel layers.

### Claim 22 (depends on 21)

The method of claim 21, further comprising:
etching the first material layers and the second material layers to form at least one second slit positioned between neighboring first source side channel layers of neighboring first channel layers, among the first channel layers, after the forming of the first channel layers and the second channel layers.

### Claim 23 (depends on 21)

The method of claim 21, further comprising:
etching the first material layers and the second material layers to form at least one fourth slit positioned between the first drain side channel layer and the second drain side channel layers, after the forming of the first channel layers and the second channel layers.

### Claim 24 (depends on 23)

The method of claim 23, wherein the fourth slit is formed to separate first material layers for drain selection lines or for drain selection lines and drain side word lines.

### Claim 25 (depends on 21)

The method of claim 21, further comprising:
etching the first material layers and the second material layers to form at least one fifth slit positioned between the first source side channel layer and the second source side channel layer, after the forming of the first channel layers and the second channel layers.

### Claim 26 (depends on 25)

The method of claim 25, wherein the fifth slit is formed to separate the first material layers for source selection lines or for source selection lines and source side word lines.