# US 2013/0153960 A1 · Anti-Fuses on Semiconductor Fins

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- Number: US 2013/0153960 A1
- Document ID: US20130153960A1
- Status: Published application
- Kind: A1
- Application number: 13/328,944
- Filed: 2011-12-16
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsiao-Lan Yang
- Web page: https://patentgrep.com/patent/US20130153960A1

## CPC

- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/0698: {Local interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.

## Claims

### Claim 1

A device comprising:
a substrate;
isolation regions at a surface of the substrate;
a semiconductor region over a top surface of the isolation regions;
a conductive feature over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region; and
a dielectric material between the conductive feature and the semiconductor region, wherein the dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.

### Claim 2 (depends on 1)

The device of claim 1 further comprising a power source coupled to the anti-fuse, wherein the power source is configured to provide a programming voltage for programming the anti-fuse.

### Claim 3 (depends on 1)

The device of claim 1, wherein the semiconductor region comprises a semiconductor fin.

### Claim 4 (depends on 1)

The device of claim 1, wherein the semiconductor region comprises an epitaxy region comprising facets that are neither parallel nor perpendicular to the top surface of the isolation regions.

### Claim 5 (depends on 4)

The device of claim 4, wherein the semiconductor region further comprises a silicide region over the epitaxy region.

### Claim 6 (depends on 4)

The device of claim 4, wherein the epitaxy region comprises silicon germanium.

### Claim 7 (depends on 1)

The device of claim 1, wherein the conductive feature comprises a semiconductor region over the top surfaces of the isolation regions, and a silicide region over the semiconductor region, and wherein a portion of the isolation regions is between the semiconductor region and the conductive feature.

### Claim 8 (depends on 1)

The device of claim 1 further comprising a multi-gate Transistor, wherein the conductive feature and a gate electrode of the multi-gate Transistor are formed of a same material.

### Claim 9

A device comprising:
a semiconductor substrate;
Shallow Trench Isolation (STI) regions at a surface of the semiconductor substrate;
a first semiconductor fin over top surfaces of the STI regions;
a second semiconductor fin over the top surfaces of the STI regions, wherein the first and the second semiconductor fins comprise facets; and
a dielectric material between the first and the second semiconductor fins, wherein the dielectric material, the first semiconductor fin, and the second semiconductor fin form an anti-fuse.

### Claim 10 (depends on 9)

The device of claim 9, wherein the first and the second semiconductor fins comprise a first silicon germanium region and a second silicon germanium region, respectively.

### Claim 11 (depends on 10)

The device of claim 10, wherein the first and the second semiconductor fins further comprises a first silicon fin and a second silicon fin underlying the first silicon germanium region and the second silicon germanium region, respectively.

### Claim 12 (depends on 11)

The device of claim 11, wherein a distance between the first silicon fin and the second silicon fin is between about 50 nm and about 70 nm.

### Claim 13 (depends on 9)

The device of claim 9, wherein the anti-fuse further comprises a first and a second silicide regions on top surfaces of the first and the second semiconductor fins, respectively.

### Claim 14 (depends on 9)

The device of claim 9 further comprising a power source coupled to the anti-fuse, wherein the power source is configured to provide a programming voltage between the first and the second semiconductor fins to program the anti-fuse from a high resistance state to a low resistance state.

### Claim 15 (depends on 9)

The device of claim 9, wherein the second semiconductor fin is aligned to a lengthwise direction of the first semiconductor fin.

### Claim 16 (depends on 9)

The device of claim 9, wherein the second semiconductor fin is on a side of the first semiconductor fin, and is not aligned to a lengthwise direction of the first semiconductor fin.

### Claim 17

A method comprising:
performing an epitaxy to form an epitaxy region over a top surface of a Shallow Trench Isolation (STI) region, wherein the STI region is at a surface of a substrate;
forming a silicide region over and contacting the epitaxy region;
forming a conductive region adjacent to the silicide region and over the STI region;
filling a dielectric material between the conductive region and a combined region of the silicide region and the epitaxy region, wherein the conductive region, the combined region, and the dielectric material form an anti-fuse; and
forming a power source electrically couple to the silicide region and the conductive region, wherein the power source is configured to apply a programming voltage high enough to program the anti-fuse.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
forming a first semiconductor fin over the top surface the STI region; and
recessing the first semiconductor fin to form a recess, wherein the epitaxy region is formed in the recess.

### Claim 19 (depends on 18)

The method of claim 18, wherein the step of forming the conductive region comprises:
forming a second semiconductor fin over the top surface the STI region;
recessing the second semiconductor fin to form an additional recess; and
simultaneously forming an additional epitaxy region in the recess at a time the step of performing the epitaxy is performed.

### Claim 20 (depends on 18)

The method of claim 18, wherein the step of forming the conductive region comprise:
forming a gate electrode layer over a gate dielectric layer, wherein the gate dielectric layer is over the first semiconductor fin; and
patterning the gate electrode layer to form a gate electrode of a multi-gate transistor and the conductive region simultaneously.