# US 2013/0153907 A1 · Thin film transistor array substrate and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0153907 A1
- Document ID: US20130153907A1
- Status: Published application
- Kind: A1
- Application number: 13/733,637
- Filed: 2013-01-03
- Published: 2013-06-20
- Earliest claimed: 2009-02-18
- Assignees: LG Display Co., Ltd.
- Inventors: Chung Wan Oh; Jae Chang Kwon; Yu Ri Shim; Chang Yeop Shin; Dong Eok Kim
- Web page: https://patentgrep.com/patent/US20130153907A1

## CPC

- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- G02F 1/13458: {Terminal pads}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring. Also, the data linker includes the gate pattern connected to the data pad, the data pattern formed opposite to the gate pattern in the center of the gate insulation film, and the connection wiring configured to connect the gate pattern with the data pattern through a first contact hole which exposes the data pattern and the gate pattern by penetrating through the passivation film and the gate insulation film.

## Claims

### Claim 1

A thin film transistor array substrate comprising:
gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions;
a thin film transistor formed at each intersection of the gate and data lines;
a passivation film formed on the thin film transistors;
a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film;
a gate pad connected to each of the gate lines through a gate linker; and
a data pad connected to each of the data lines through a data linker,
wherein the data pad is formed of a gate pattern, the data line is formed of a data pattern, the data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring and include the gate pattern connected to the data pad, the data pattern formed opposite to the gate pattern in the center of the gate insulation film, and the connection wiring configured to connect the gate pattern with the data pattern through a first contact hole which exposes the data pattern and the gate pattern by penetrating through the passivation film and the gate insulation film,
wherein the whole of the data pattern is overlapped with a part of the gate pattern, and
wherein the first contact hole is formed in a center area of the gate pattern,
a second contact hole formed to penetrate through the passivation film and the gate insulation film and expose the gate pattern.

### Claim 2 (depends on 1)

The thin film transistor array substrate claimed as claim 1, wherein the connection wiring is configured to individually pass through the first and second contact holes.

### Claim at position 3

3-10. (canceled)