# US 2013/0153899 A1 · Semiconductor device having plural semiconductor chips

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- Number: US 2013/0153899 A1
- Document ID: US20130153899A1
- Status: Published application
- Kind: A1
- Application number: 13/720,875
- Filed: 2012-12-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Elpida Memory, Inc.
- Inventors: Shoji WADA; Toru ISHIKAWA
- Web page: https://patentgrep.com/patent/US20130153899A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal.

## Claims

### Claim 1

A semiconductor device comprising:
a first chip including first and second surfaces opposed to each other, first, second and third terminals on the first surface, and a fourth terminal on the second surface, the first and fourth terminals being electrically coupled to each other through a penetration electrode penetrating a semiconductor substrate of the first chip, and a first internal node of which an electrical potential being changed in response to an electrical potential of the first terminal; and
a second chip stacked with the first chip, the second chip including a third surface facing to the second surface of the first chip, a fourth surface opposed to the third surface, a fifth terminal on the third surface electrically coupled to the fourth terminal of the first chip, sixth and seventh terminals on the third surface, and a second internal node of which an electrical potential being changed in response to an electrical potential of the fifth terminal;
the first internal node of the first chip being electrically coupled to both the second terminal of the first chip and the sixth terminal of the second chip, the second internal node of the second chip being electrically coupled to both the third terminal of the first chip and the seventh terminal of the second chip.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first, fourth and fifth terminals are arranged in line in a first direction perpendicular in common to the first, second, third and fourth surfaces, the second and seventh terminals being arranged in line in the first direction, and the third and sixth terminals being arranged in line in the first direction.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the second chip further includes a memory circuit and a test circuit electrically coupled to the fifth terminal, the test circuit performing a test operation on the memory circuit in response to a test signal supplied from the fifth terminal.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a controller chip on which the first and second chips are mounted, wherein each of the first and second chips includes a memory circuit and the controller chip is configured to perform a read/write operation on the memory circuit of each of the first and second chips.

### Claim 5 (depends on 4)

The semiconductor device as claimed in claim 4, further comprising a package board including a fifth surface on which the controller chips and the first and second chips are mounted, a sixth surface opposed to the fifth surface, and a plurality of solder balls on the sixth surface, the solder balls being electrically coupled to the controller chip, the controller chip being configured to perform the read/write operation on the memory circuit of each of the first and second chips in response to control signals supplied with the solder balls.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the first, second, third and fourth terminals of the first chip are electrically independent of each of the solder balls.

### Claim 7 (depends on 6)

The semiconductor device as claimed in claim 6, wherein the fifth, sixth and seventh terminals of the second chip are electrically independent of each of the solder balls.