# US 2013/0153898 A1 · Semiconductor device having plural semiconductor chip stacked with one another

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- Number: US 2013/0153898 A1
- Document ID: US20130153898A1
- Status: Published application
- Kind: A1
- Application number: 13/720,863
- Filed: 2012-12-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Elpida Memory, Inc.
- Inventors: Tetsuji TAKAHASHI; Toru ISHIKAWA
- Web page: https://patentgrep.com/patent/US20130153898A1

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 90/00: Package configurations
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal.

## Claims

### Claim 1

A device comprising:
a plurality of external terminals including first and second external terminals;
a first semiconductor chip including a plurality of control circuits that comprises a first control circuit, the first control circuit generating a first control signal; and
a second semiconductor chip stacked with the first semiconductor chip, the second semiconductor chip comprising;
a first test terminal configured to be supplied with a first test signal, the first test terminal being free from connecting to any one of the external terminals;
a second test terminal configured to be supplied with the first test signal, the second test terminal being coupled to the first external terminal without connecting to any one of control circuits of the first semiconductor chip;
a first normal terminal configured to be supplied with the first control signal, the first normal terminal being coupled to the second external terminal with an intervention of the first control circuit of the first semiconductor chip; and
a first selection circuit including first and second input nodes, the first input node being coupled in common to the first and second test terminals and the second input node being coupled to the first normal terminal.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein the second semiconductor chip further comprises a first test input buffer coupled in common to the first and second test terminals at an input node thereof and coupled to the first input node of the first selection circuit at an output node thereof.

### Claim 3 (depends on 1)

The device as claimed in claim 1, wherein the second semiconductor chip further comprises first and second test input buffers, the first test input buffer is coupled to the first test terminal at an input node thereof, the second test input buffer is coupled to the second test terminal at an input node thereof, and the first input node of the first selection circuit is coupled in common to output nodes of the first and second test input buffers.

### Claim 4 (depends on 1)

The device as claimed in claim 1, wherein the control circuits of the first semiconductor chip comprises a plurality of second control circuits generating a plurality of second control signals, and the second semiconductor chip further comprises;
a plurality of second normal terminals each configured to be supplied with an associated one of the second control signals, and
a plurality of second selection circuits each including first and second input nodes, the first input node of each of the second selection circuits being coupled in common to the first and second test terminals, and the second input node of each of the second selection circuits being coupled to an associated one of the second normal terminals.

### Claim 5 (depends on 4)

The device as claimed in claim 4, wherein the second semiconductor chip further comprises;
a first channel comprising the first selection circuit, and
a plurality of second channel each comprising an associated one of the second selection circuits, and
the first and second internal devices are configured to operate independently of each other.

### Claim 6 (depends on 5)

The device as claimed in claim 5, wherein each of the first and second channels is configured to operate as DRAM.

### Claim 7 (depends on 1)

The device as claimed in claim 1, wherein the first semiconductor chip further comprises;
a semiconductor substrate,
a first penetration electrode penetrating through the semiconductor substrate and being free from connecting to any one of the control circuits, the first penetration electrode being coupled to the second test terminal of the second semiconductor chip, and
a second penetration electrode penetrating through the semiconductor substrate and coupled to the first control circuit, the second penetration electrode being coupled to the first normal terminal of the second semiconductor chip.

### Claim 8 (depends on 1)

The device as claimed in claim 1, wherein the second semiconductor chip further comprises;
a semiconductor substrate,
a first test penetration electrode penetrating through the semiconductor substrate and coupled to the second test terminal, and
a first normal penetration electrode penetrating through the semiconductor substrate and coupled to the first normal terminal.

### Claim 9 (depends on 1)

The device as claimed in claim 1, wherein the first test terminal is a test pad, each of the second test terminal and the first normal terminal is a bump electrode.

### Claim 10 (depends on 1)

The device as claimed in claim 1, wherein the first test terminal is a test pad, each of the second test terminal and the first normal terminal is a bonding pad coupled to a bonding wiring.

### Claim 11 (depends on 1)

The device as claimed in claim 1, wherein the first test signal includes one of a test address signal, a test command signal and a test clock signal, and the first control signal includes one of a normal address signal, a normal command signal and a normal clock signal.

### Claim 12

A device comprising:
a first test pad;
a first test bump electrode;
a first normal bump electrode;
a first test input buffer coupled in common to the first test pad and the first test bump electrode at an input node thereof; and
a first normal input buffer coupled to the first normal bump electrode at an input node thereof.

### Claim 13 (depends on 12)

The device as claimed in claim 12, further comprising;
a plurality of second normal bump electrodes,
a plurality of second normal input buffers each coupled to an associated one of the second normal bump electrodes at input node thereof, and
a plurality of channels configured to operate independently of each other, and
wherein the first test input buffer is coupled in common to the channels at an output node thereof, and each of the first and second normal input buffers is coupled to a corresponding one of the channels at an output node thereof.

### Claim 14 (depends on 13)

The device as claimed in claim 13, wherein each of the channel comprising;
a memory cell array, and
an access control circuit coupled to the first test buffer and an associated one of the first and second normal input buffers, the access control circuit performing an operation on the memory cell array.

### Claim 15 (depends on 13)

The device as claimed in claim 13, wherein each of the channels is configured to operate as a DRAM.

### Claim 16 (depends on 12)

The device as claimed in claim 12, further comprising;
a semiconductor substrate, and
a plurality of penetration electrodes each penetrating through the semiconductor substrate, the penetration electrodes comprising a first test penetration electrode and a first normal penetration electrode, and
wherein the first test penetration electrode is coupled to the first test bump electrode and the first normal penetration electrode is coupled to the first normal bump electrode.

### Claim 17 (depends on 12)

The device as claimed in claim 12, further comprising a first selection circuit including first and second input nodes, and wherein the first test input buffer coupled to the first input node of the first selection circuit at an output node thereof, and the first normal input buffer coupled to the second input node of the first selection circuit.

### Claim 18 (depends on 12)

The device as claimed in claim 12, further comprising;
a plurality of external terminals including first and second external terminals,
a first semiconductor chip stacked with the first semiconductor chip, the second semiconductor chip including the first test pad, the first bump electrode, the first normal bump electrode, the first test input buffer and the first normal input buffer, and
wherein the first test bump electrode is coupled to the first external terminal, the first normal bump electrode is coupled to the second external terminal.

### Claim 19 (depends on 18)

The device as claimed in claim 18, wherein the first test pad is free from connecting to any one of the external terminals.

### Claim 20 (depends on 12)

The device as claimed in claim 12, wherein each of the first test pad and the first test bump electrode is configured to be supplied with one of a test address signal, a test command signal and a test clock signal, and the first normal bump electrode is configured to be supplied with one of a normal address signal, a normal command signal and a normal clock signal.