# US 2013/0153894 A1 · Semiconductor device

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- Number: US 2013/0153894 A1
- Document ID: US20130153894A1
- Status: Published application
- Kind: A1
- Application number: 13/767,904
- Filed: 2013-02-15
- Published: 2013-06-20
- Earliest claimed: 2010-07-02
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Kiyoshi Kato
- Web page: https://patentgrep.com/patent/US20130153894A1

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/30: characterised by the memory core region
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10B 99/22: {including field-effect components}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

## Claims

### Claim 1

A semiconductor device comprising:
a first transistor comprising a first channel formation region comprising a single crystal silicon;
a second transistor comprising a second channel formation region comprising an oxide semiconductor material, over the first transistor;
a capacitor over the first transistor; and
a third transistor comprising a third channel formation region comprising the oxide semiconductor material, over the second transistor,
wherein the third transistor overlaps with at least one of the first transistor and the second transistor,
wherein a gate of the first transistor is electrically connected to one of a source or a drain of the second transistor and the capacitor, and
wherein the oxide semiconductor material comprises Indium.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein one of a source or a drain of the first transistor is electrically connected to the other one of the source or the drain of the second transistor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the gate of the first transistor is in contact with the one of the source or the drain of the second transistor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the third transistor overlaps with the first transistor and the capacitor.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the oxide semiconductor material further comprises gallium and zinc.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein off-state current of the second transistor is lower than or equal to 1×10−19 A at 25° C.

### Claim 7

A semiconductor device comprising:
a first transistor comprising a first channel formation region comprising a single crystal silicon;
a second transistor over the first transistor, the second transistor comprising:
an oxide semiconductor layer comprising a second channel formation region, the second channel formation region comprising an oxide semiconductor material;
a source and a drain over the oxide semiconductor layer;
a gate insulating layer over the source and the drain; and
a gate over the gate insulating layer, the gate overlapping with the source and the drain,
a capacitor over the first transistor; and
a third transistor comprising a third channel formation region comprising the oxide semiconductor material, over the second transistor,
wherein the third transistor overlaps with at least one of the first transistor and the second transistor,
wherein a gate of the first transistor is electrically connected to one of the source or the drain of the second transistor and the capacitor, and
wherein the oxide semiconductor material comprises Indium.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein one of a source or a drain of the first transistor is electrically connected to the other one of the source or the drain of the second transistor.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein the gate of the first transistor is in contact with the one of the source or the drain of the second transistor.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7, wherein the third transistor overlaps with the first transistor and the capacitor.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7, wherein the oxide semiconductor material further comprises gallium and zinc.

### Claim 12 (depends on 7)

The semiconductor device according to claim 7, wherein off-state current of the second transistor is lower than or equal to 1×10−19 A at 25° C.

### Claim 13

A semiconductor device comprising:
a first transistor comprising a first channel formation region comprising a single crystal silicon;
a second transistor comprising a second channel formation region comprising an oxide semiconductor material, over the first transistor;
a first capacitor over the first transistor;
a third transistor comprising a third channel formation region comprising the oxide semiconductor material, over the second transistor;
a fourth transistor comprising a fourth channel formation region comprising the oxide semiconductor material, over the third transistor; and
a second capacitor over the third transistor,
wherein the third transistor overlaps with at least one of the first transistor and the second transistor,
wherein a gate of the first transistor is electrically connected to one of a source or a drain of the second transistor and the first capacitor, and
wherein the oxide semiconductor material comprises Indium.

### Claim 14 (depends on 13)

The semiconductor device according to claim 13, wherein one of a source or a drain of the first transistor is electrically connected to the other one of the source or the drain of the second transistor.

### Claim 15 (depends on 13)

The semiconductor device according to claim 13, wherein the gate of the first transistor is in contact with the one of the source or the drain of the second transistor.

### Claim 16 (depends on 13)

The semiconductor device according to claim 13, wherein the third transistor overlaps with the first transistor and the first capacitor.

### Claim 17 (depends on 13)

The semiconductor device according to claim 13, wherein the fourth transistor overlaps with the third transistor.

### Claim 18 (depends on 13)

The semiconductor device according to claim 13, wherein a gate of the third transistor is electrically connected to one of a source or a drain of the fourth transistor and the second capacitor.

### Claim 19 (depends on 13)

The semiconductor device according to claim 13, wherein the oxide semiconductor material further comprises gallium and zinc.

### Claim 20 (depends on 13)

The semiconductor device according to claim 13, wherein off-state current of the second transistor is lower than or equal to 1×10−19 A at 25° C.