# US 2013/0153891 A1 · Thin film transistor and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0153891 A1 - Document ID: US20130153891A1 - Status: Published application - Kind: A1 - Application number: 13/711,540 - Filed: 2012-12-11 - Published: 2013-06-20 - Earliest claimed: 2011-12-14 - Assignees: E Ink Holdings Inc. - Inventors: Hsiao-Wen ZAN; Chuang-Chuang TSAI; Chun-Hung LIAO; Wei-Tsung CHEN - Web page: https://patentgrep.com/patent/US20130153891A1 ## CPC - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Disclosed herein is a thin film transistor, which includes a metal oxide semiconductor layer, an insulating layer, a gate electrode, a source electrode and a drain electrode. The metal oxide semiconductor layer includes a channel region having at least one first region and a second region. The first region has an oxygen vacancy concentration greater than an oxygen vacancy concentration of the second region. The second region surrounds the first region. A method for manufacturing the thin film transistor is disclosed as well. ## Claims ### Claim 1 A thin film transistor, comprising: a metal oxide semiconductor layer comprising: a channel region having at least one first region and a second region, wherein the first region has an oxygen vacancy concentration greater than an oxygen vacancy concentration of the second region, wherein the first region is surrounded by the second region; and a source region and a drain region respectively disposed at opposite sides of the channel region; an first insulating layer disposed on the channel region: a first gate electrode disposed on the first insulating layer and having at least one first opening positioned above the first region; and a source electrode and a drain electrode respectively connected electrically to the source region and the drain region. ### Claim 2 (depends on 1) The thin film transistor according to claim 1, wherein the channel region has a plurality of the first regions, and each of the first regions is spaced apart from another one of the first regions. ### Claim 3 (depends on 2) The thin film transistor according to claim 2, wherein the first gate electrode has a plurality of the first openings penetrating the first gate electrode, and each of the first openings is positioned right above a corresponding one of the first regions. ### Claim 4 (depends on 3) The thin film transistor according to claim 3, wherein each of the first openings has a contour that is substantially the same as a contour of the corresponding one of the first regions. ### Claim 5 (depends on 3) The thin film transistor according to claim 3, wherein the first insulating layer has a plurality of second openings penetrating the first insulating layer, and each of the second openings is substantially aligned with a corresponding one of the first openings. ### Claim 6 (depends on 2) The thin film transistor according to claim 2, wherein each of the first regions has a width of about 1 nm to about 1 μm. ### Claim 7 (depends on 2) The thin film transistor according to claim 2, wherein each of the first regions has a geometry center, and a distance between any two adjacent geometry centers is about 51 nm to about 1500 nm. ### Claim 8 (depends on 2) The thin film transistor according to claim 2, wherein a spacing interval between any two adjacent first regions is about 50 nm to about 500 nm. ### Claim 9 (depends on 2) The thin film transistor according to claim 2, wherein the first regions are arranged in a number density of about 1×106 mm−2 to about 1×107 mm−2. ### Claim 10 (depends on 1) The thin film transistor according to claim 1, wherein a ratio of the oxygen vacancy concentration of the first region to the oxygen vacancy concentration of the second region ranges from about 1.1 to about 1.3. ### Claim 11 (depends on 1) The thin film transistor according to claim 1, wherein the metal oxide semiconductor layer comprises indium gallium zinc oxide (IGZO). ### Claim 12 (depends on 1) The thin film transistor according to claim 1, further comprising a second gate electrode and a second insulating layer, wherein the first and second gate electrodes are respectively disposed at opposite sides of the metal oxide semiconductor layer, and the second insulating layer is positioned between the second gate electrode and the metal oxide semiconductor layer. ### Claim 13 (depends on 12) The thin film transistor according to claim 12, further comprising a substrate, wherein the second gate electrode is disposed on the substrate, the second insulating layer covers the second gate electrode, and the metal oxide semiconductor layer is positioned on the second insulating layer. ### Claim 14 (depends on 12) The thin film transistor according to claim 12, wherein the second gate electrode overlaps the first gate electrode in a direction perpendicular to the metal oxide semiconductor layer. ### Claim 15 (depends on 12) The thin film transistor according to claim 12, wherein the second gate electrode has an area that is greater than or equal to an area of the first gate electrode. ### Claim 16 (depends on 1) The thin film transistor according to claim 1, wherein the first opening has a contour that is substantially the same as a contour of the first region. ### Claim 17 (depends on 1) The thin film transistor according to claim 1, wherein the first insulating layer has at least one second opening penetrating the first insulating layer, and the second opening is substantially aligned with the first opening. ### Claim 18 A method for manufacturing a thin film transistor, comprising: (a) forming a metal oxide semiconductor layer on a substrate, the metal oxide semiconductor layer having an initial oxygen vacancy concentration; (b) forming a first insulating layer on the metal oxide semiconductor layer; (c) forming a first patterned conductive layer on the first insulating layer, wherein the first patterned conductive layer has at least one first opening, and a projection of the first opening onto the substrate overlaps a projection of the metal oxide semiconductor layer onto the substrate; (d) treating the metal oxide semiconductor layer to form a channel region having at least one first region by using the first patterned conductive layer as a mask such that the first region has an oxygen vacancy concentration greater than the initial oxygen vacancy concentration; and (e) forming a source electrode and a drain electrode respectively on opposite sides of the channel region. ### Claim 19 (depends on 18) The method according to claim 18, wherein the step (c) comprises patterning the first insulating layer to form at least one second opening penetrating the first insulating layer, and the second opening is substantially aligned with the first opening. ### Claim 20 (depends on 19) The method according to claim 19, wherein the step (c) comprises forming a plurality of the first opening and forming a plurality of the second opening. ### Claim 21 (depends on 20) The method according to claim 20, wherein each of the first openings has a width of about 1 nm to about 1 μm. ### Claim 22 (depends on 18) The method according to claim 18, wherein the step (d) comprises forming a plurality of the first regions, and each of the first regions has a geometry center, and a distance between any two adjacent geometry centers is about 51 nm to about 1500 nm. ### Claim 23 (depends on 18) The method according to claim 18, wherein the step (d) comprises forming a plurality of the first regions, and a spacing interval between any two adjacent first regions is about 50 nm to about 500 nm. ### Claim 24 (depends on 18) The method according to claim 18, wherein the step (d) comprises forming a plurality of the first regions, and the first regions of the channel region are formed in a number density of about 1×106 mm−2 to about 1×107 mm−2. ### Claim 25 (depends on 18) The method according to claim 18, wherein a ratio of the oxygen vacancy concentration of the first region in the step (e) to the initial oxygen vacancy concentration ranges from about 1.1 to about 1.3. ### Claim 26 (depends on 18) The method according to claim 18, wherein the metal oxide semiconductor layer of the step (a) comprises indium gallium zinc oxide (IGZO). ### Claim 27 (depends on 18) The method according to claim 18, wherein the step (c) comprises: (c1) forming a conductive layer on the first insulating layer; (c2) forming a polymer layer on the conductive layer; (c3) imprinting the polymer layer by a patterned mode to form a patterned polymer layer; (c4) treating the patterned polymer layer by plasma to reduce a thickness of the patterned polymer layer, and thereby forming a resist layer having a plurality of apertures exposing a portion of the conductive layer; (c5) removing the exposed portion of the conductive layer and a portion of the first insulating layer there under by using the resist layer as a mask to form the first patterned conductive layer and at least one second opening penetrating the first insulating layer, wherein the second opening is substantially aligned with the first opening; and (c6) removing the resist layer after the step (c5). ### Claim 28 (depends on 18) The method according to claim 18, wherein the step (c) comprises removing a portion of the first insulating layer, and thus allowing a source region and a drain region of the metal oxide semiconductor layer to be exposed. ### Claim 29 (depends on 28) The method according to claim 28, wherein the step (d) comprises treating the source region and the drain region such that each of the source region and the drain region has an oxygen vacancy concentration that is greater than the initial oxygen vacancy concentration, and the step (e) comprises forming the source electrode and the drain electrode respectively on the treated source region and the treated drain region. ### Claim 30 (depends on 18) The method according to claim 18, wherein, in the step (a), the substrate comprises a second conductive layer and a second insulating layer covering the second conductive layer, and the metal oxide semiconductor layer is formed on the second insulating layer.