# US 2013/0153887 A1 · Semiconductor device and method of manufacturing the semiconductor device

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- Number: US 2013/0153887 A1
- Document ID: US20130153887A1
- Status: Published application
- Kind: A1
- Application number: 13/680,757
- Filed: 2012-11-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Renesas Electronics Corporation
- Inventors: Kishou KANEKO; Naoya INOUE; Yoshihiro HAYASHI
- Web page: https://patentgrep.com/patent/US20130153887A1

## CPC

- H10D 86/021: {of multiple TFTs}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P 95/70: Chemical treatments
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

## Claims

### Claim 1

A semiconductor device comprising:
a multilayer interconnect layer having a first interconnect layer and a second interconnect layer positioned over the first interconnect layer; and
a first transistor and a second transistor formed by using the first interconnect layer,
wherein the first transistor includes:
a first gate electrode buried in the first interconnect layer;
a first gate insulating film positioned over the first gate electrode;
a first semiconductor layer positioned over the first gate insulating film; and
an insulating cover film positioned below the second interconnect layer and covering the upper surface and the lateral side of the first semiconductor layer, and
wherein the second transistor includes:
a second gate electrode buried in the first interconnect layer;
a second gate insulating film positioned over the second gate electrode; and
a second semiconductor layer positioned over the second gate insulating film, positioned at least partially above the insulating cover film and formed of a material different from that of the first semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the multilayer interconnect layer has an anti-diffusion film positioned between the first interconnect layer and the second interconnect layer, and
wherein the first gate insulating film and the second gate insulating film contain the anti-diffusion film.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein the insulating cover film is positioned also below the semiconductor layer, and
wherein the second insulating film has the insulating cover film positioned below the second semiconductor layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the multilayer interconnect layer has an anti-diffusion film positioned between the first interconnect layer and the second interconnect layer,
wherein the anti-diffusion film has a first opening positioned over the first gate electrode, and
wherein the first gate insulating film is positioned in the first opening.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein the multilayer interconnect layer has an anti-diffusion film positioned between the first interconnect layer and the second interconnect layer,
wherein the insulating cover film is formed also over the anti-diffusion film,
wherein a stacked film of the anti-diffusion film and the insulating cover film has a second opening positioned over the second gate electrode, and
wherein the second gate insulating film is positioned in the second opening.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein the film thickness is different between the first gate insulating film and the second gate insulating film.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein the conduction type of the first semiconductor layer and the second semiconductor layer is different from each other.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1,
wherein the conduction type of the first semiconductor layer and the second semiconductor layer is identical to each other.

### Claim 9 (depends on 1)

A semiconductor device according to claim 1, wherein
the insulating cover film contains one of SiN film, SiO2 film, SiOC film, and SiOCH film.

### Claim 10 (depends on 2)

The semiconductor device according to claim 2,
wherein the anti-diffusion film contains at least one of SiN film, SiCN film, and SiC film.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1,
wherein each of the first gate electrode and the second gate electrode comprises a Cu interconnect.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1,
wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor layer.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12,
wherein the oxide semiconductor layer is, InGaZnO layer, InZnO layer, ZnO layer, ZnAlO layer, ZnCuO layer, NiO layer, SnO layer, SnO2 layer, CuO layer, Cu2O layer, CuAlO layer, ZnO layer, ZnAlO layer, Ta2O5 layer, or TiO2 layer.

### Claim 14

A method of manufacturing a semiconductor device comprising:
forming a first interlayer insulating film;
burying a first gate electrode and a second gate electrode in the first interlayer insulating film;
forming a first gate insulating film and a first semiconductor layer over the first gate electrode;
forming an insulating cover film over the upper surface and on the lateral side of the first semiconductor layer;
forming a second semiconductor layer over the insulating cover film and over the second gate electrode; and
selectively removing the semiconductor layer thereby leaving a portion of the second semiconductor layer that is positioned over the second gate electrode.