# US 2013/0153858 A1 · Nitride semiconductor template and light-emitting diode

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0153858 A1
- Document ID: US20130153858A1
- Status: Published application
- Kind: A1
- Application number: 13/714,300
- Filed: 2012-12-13
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Hitachi Cable, Ltd.
- Inventors: Taichiroo Konno; Hajime Fujikura
- Web page: https://patentgrep.com/patent/US20130153858A1

## CPC

- H10D 62/60: Impurity distributions or concentrations
- H10H 20/8215: {characterised by crystalline imperfections, e.g. dislocations; characterised by the distribution of dopants, e.g. delta-doping}
- H10H 20/8252: {characterised by the dopants}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2921: {being crystalline insulating materials}
- H10P 14/2925: {Surface structures}
- H10P 14/3216: {Nitrides}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3416: {Nitrides}
- H10P 14/3441: {Conductivity type}
- H10P 14/3442: {N-type}
- H10H 20/812: within the light-emitting regions, e.g. having quantum confinement structures
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A nitride semiconductor template includes a substrate, and a group III nitride semiconductor layer formed on the substrate and including a Si-doped layer doped with Si as an uppermost layer thereof. The group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm. The Si-doped layer includes a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×1017 cm−3 and not more than 5×1017 cm−3 at the outermost surface of the group III nitride semiconductor layer.

## Claims

### Claim 1

A nitride semiconductor template, comprising:
a substrate; and
a group III nitride semiconductor layer formed on the substrate and comprising a Si-doped layer doped with Si as an uppermost layer thereof,
wherein the group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm, and
wherein the Si-doped layer comprises a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×1017 cm−3 and not more than 5×1017 cm−3 at the outermost surface of the group III nitride semiconductor layer.

### Claim 2 (depends on 1)

The nitride semiconductor template according to claim 1, wherein the group III nitride semiconductor layer comprises an O-doped layer doped with O (oxygen) between the substrate and the Si-doped layer.

### Claim 3 (depends on 2)

The nitride semiconductor template according to claim 2, wherein the O-doped layer has an O-impurity concentration of not less than 1×1016 cm−3 and not more than 3×1019 cm−3 and an average carrier concentration in a thickness direction of not less than 8×1017 cm−3 and not more than 1×1018 cm−3.

### Claim 4 (depends on 1)

The nitride semiconductor template according to claim 1, wherein the Si-doped layer comprises a high Si concentration layer having a uniform carrier concentration in a thickness direction, and
wherein the Si concentration gradient layer has a carrier concentration that gradually decreases from the high Si concentration layer toward the outermost surface.

### Claim 5 (depends on 4)

The nitride semiconductor template according to claim 4, wherein the carrier concentration of the high Si concentration layer is not less than 1×1017 cm−3 and not more than 1×1019 cm−3.

### Claim 6 (depends on 1)

The nitride semiconductor template according to claim 1, wherein the substrate comprises a PSS (Patterned Sapphire Substrate) comprising a plurality of convex portions on a surface thereof.

### Claim 7 (depends on 1)

The nitride semiconductor template according to claim 1, wherein the template has a surface resistivity of not less than 10 Ω/sq and not more than 30 Ω/sq.

### Claim 8 (depends on 1)

The nitride semiconductor template according to claim 1, wherein the template has a half-value width at a (0004) plane of not more than 100 seconds by X-ray diffraction measurement.

### Claim 9

A light-emitting diode, comprising:
a sapphire substrate;
an AlN buffer layer formed on the sapphire substrate;
an n-type group III nitride semiconductor layer formed on the AlN buffer layer;
a multiple quantum well layer formed on the n-type group III nitride semiconductor layer;
a p-type nitride semiconductor layer formed on the multiple quantum well layer;
an exposed portion of the n-type group III nitride semiconductor layer formed by etching from the p-type nitride semiconductor layer to the n-type group III nitride semiconductor layer;
an n-type electrode formed on the exposed portion of the n-type group III nitride semiconductor layer; and
a p-type electrode formed on the p-type nitride semiconductor layer,
wherein the n-type group III nitride semiconductor layer comprises a group III nitride semiconductor layer comprising a Si-doped layer doped with Si as an uppermost layer thereof,
wherein the group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm, and
wherein the Si-doped layer comprises a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×1017 cm−3 and not more than 5×1017 cm−3 at the outermost surface of the group III nitride semiconductor layer.