# US 2013/0153852 A1 · Variable resistance memory devices and methods of forming the same

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- Number: US 2013/0153852 A1
- Document ID: US20130153852A1
- Status: Published application
- Kind: A1
- Application number: 13/690,575
- Filed: 2012-11-30
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Inventors: Jintaek Park; Youngwoo Park
- Web page: https://patentgrep.com/patent/US20130153852A1

## CPC

- H10N 70/20: Multistable switching devices, e.g. memristors
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A variable resistance memory device comprises a bit line extended in a first direction, a vertical electrode extended vertically in a third direction and configured to be vertically aligned with the bit line in the third direction, a variable resistance layer disposed on a part of the vertical electrode, multiple word lines disposed on the variable resistance layer and stacked in the third direction, wherein each of multiple word lines are extended in a second direction, and a selection transistor including a first dopant injection region electrically connected to the vertical electrode, and a second dopant injection region electrically connected to the bit line.

## Claims

### Claim 1

A variable resistance memory device comprising:
a bit line extended in a first direction;
a vertical electrode extended vertically in a third direction and configured to be vertically aligned with the bit line;
a variable resistance layer disposed on a part of the vertical electrode;
multiple word lines disposed on the variable resistance layer and stacked in the third direction, wherein each of multiple word lines are extended in a second direction; and
a selection transistor including a first dopant injection region electrically connected to the vertical electrode and a second dopant injection region electrically connected to the bit line.

### Claim 2 (depends on 1)

The variable resistance memory device of claim 1, further comprising:
an active pattern disposed over the bit line, wherein the first dopant injection region and the second dopant injection region are disposed in the active pattern; and
a bit line node contact disposed on the bit line, being electrically connected with the second dopant injection region.

### Claim 3 (depends on 2)

The variable resistance memory device of claim 2, wherein the vertical electrode includes a first sub-vertical electrode disposed on the first dopant injection region, a first pad disposed on the first sub-vertical electrode and a second sub-vertical electrode disposed on the pad.

### Claim 4 (depends on 3)

The variable resistance memory device of claim 3, further comprising:
a second pad disposed over the bit line node contact wherein the second pad has a line shape extended in the first direction.

### Claim 5 (depends on 2)

The variable resistance memory device of claim 2, wherein the bit line node contact is configured to penetrate the active pattern and has a top surface substantially coplanar with a top surface of the active pattern.

### Claim 6 (depends on 2)

The variable resistance memory device of claim 2, wherein the bit line node contact is configured to be in contact with a bottom surface of the active pattern.

### Claim 7 (depends on 1)

The variable resistance memory device of claim 1, further comprising:
an active pattern disposed under the bit line, wherein the first dopant injection region and the second injection region are disposed in the active pattern; and
a bit line node contact disposed on the second dopant injection region, electrically being connected with the bit line.

### Claim 8 (depends on 7)

The variable resistance memory device of claim 7, wherein the active pattern is disposed over the multiple word lines and the vertical electrode includes a first sub-vertical electrode and a second sub-vertical electrode, the first sub-vertical electrode penetrating the first dopant injection region and a second sub-vertical electrode being disposed on the first sub-vertical electrode and adjacent to the multiple word lines.

### Claim 9 (depends on 7)

The variable resistance memory device of claim 7, wherein the first and second dopant injection regions are disposed in a substrate, and the bit line node contact includes a first bit line node contact disposed on the second dopant injection region, a second bit line node contact disposed on the first bit line node contact disposed on the bit line, and a second pad connecting the first bit line node and the second bit line node.

### Claim 10 (depends on 7)

The variable resistance memory device of claim 7, wherein the multiple word lines are disposed between the bit line and the active pattern, and the bit line node contact includes a first bit line node contact disposed on the second dopant injection region, a second bit line node contact disposed on the first bit line node contact disposed on the bit line, and a second pad connecting the first bit line node and the second bit line node.

### Claim 11 (depends on 1)

The variable resistance memory device of claim 1, further comprising:
a peripheral circuit disposed under the vertical electrode and the bit line,
wherein the peripheral circuit controls voltages applied to the word lines, the bit line, and the selection transistor.

### Claim 12 (depends on 1)

The variable resistance memory device of claim 1, wherein end portions of the word lines constitute a stepped structure.

### Claim 13 (depends on 1)

The variable resistance memory device of claim 1, wherein each of the multiple word lines includes two groups of word lines on a same cell layer and each group of word lines includes a plurality of word lines connected to each other.

### Claim 14 (depends on 1)

The variable resistance memory device of claim 1, wherein the selection transistor includes a gate electrode having a line-shape extended in the first direction in a plan view and being disposed over the bit line.

### Claim 15 (depends on 1)

The variable resistance memory device of claim 1, wherein the first dopant injection region includes a first low-concentration dopant injection region adjacent to one side of the gate electrode and a first high-concentration dopant injection region separated from the one side of the gate electrode; and
wherein the second dopant injection region includes a second low-concentration dopant injection region adjacent to another side of the gate electrode and a second high-concentration dopant injection region separated from the another side of the gate electrode.

### Claim at position 16

16-20. (canceled)