# US 2013/0153848 A1 · Semiconductor memory device and method of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0153848 A1
- Document ID: US20130153848A1
- Status: Published application
- Kind: A1
- Application number: 13/489,753
- Filed: 2012-06-06
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Inventors: Nam Kyun PARK; Kang Sik CHOI
- Web page: https://patentgrep.com/patent/US20130153848A1

## CPC

- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/841: {Electrodes}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory device, comprising:
forming a gate cell material layer on a bit line;
etching a portion of the gate cell material layer in a line shape in a direction that the bit line extends to form a line shape etched region;
forming a first spacer insulating layer in the line shape etched region;
performing an etch-back process on the first spacer insulating layer to expose the bit line and form an etch-back region;
forming a first oxide layer below the first spacer insulating layer;
forming a first buried insulating layer in the etch-back region;
etching the gate cell material layer in a direction perpendicular to the direction that the bit line extends to form a first trench;
forming a second spacer insulating layer in the first trench on sidewalls of the gate cell material layer;
performing an etch-back process on the second spacer insulating layer to expose the bit line;
forming a second oxide layer below the second spacer insulating layer;
forming a second buried insulating layer in the first trench;
removing the first spacer insulating layer and the second spacer insulating layer;
sequentially forming a gate oxide layer and a gate metal layer in a space formed by removing the first and second spacer insulating layer;
removing a portion of the gate oxide layer and the gate metal layer;
forming a third buried insulating layer in a space formed by removing the portion of the gate oxide layer and the gate metal layer;
removing an upper portion of the gate cell material layer;
sequentially forming a lower electrode and a data storage material layer in a space formed by removing the upper portion of the gate cell material layer; and
forming an interconnection layer on the data storage material layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the gate cell material layer includes a semiconductor material selected from the group consisting of silicon (Si), silicon germanium (Site), germanium (Ge), and gallium arsenide (GaAs).

### Claim 3 (depends on 2)

The method of claim 2, wherein the gate cell material layer includes a semiconductor material selected from the group consisting of an N-doped semiconductor material, a P-doped semiconductor material, and an undoped semiconductor material to form a source, a drain, and a channel in a direction perpendicular to the direction that the bit line extends.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming a silicide layer using a material selected from titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), platinum (Pt), lead (Pb), molybdenum (Mo) and tantalum (Ta) at an interface between the lower electrode and the gate cell material layer to reduce a contact resistance between the lower electrode and the gate cell material layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the data storage layer includes a resistive layer for constituting any one selected from the group consisting of a phase-change random access memory (PCRAM), a magnetic random access memory (MRAM), a spin-transfer torque MRAM (STTMRAM), and a polymer random access memory (PoRAM).

### Claim 6 (depends on 5)

The method of claim 5, wherein, when the data storage material layer includes a material for the PCRAM, the data storage material layer includes a material layer selected from tellurium (Te), selenium (Se), germanium (Ge), a compound thereof, and an alloy thereof.

### Claim 7 (depends on 6)

The method of claim 6, wherein the data storage material layer includes a material selected from the group consisting of Te, Se, Ge, bismuth (Bi), Pb, tin (Sn), arsenic (As), sulfur (S), Si, phosphorus (P), oxygen (O), nitrogen (N), a compound thereof, and an alloy thereof.

### Claim 8 (depends on 1)

The method of claim 1, wherein each of the bit line, the gate metal layer, the lower electrode, and the interconnection layer includes at least one of a metal, an alloy, a metal oxinitride, and a conductive carbon compound including tungsten (W), copper (Cu), titanium nitride (TIN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoAlN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TIAION), tungsten oxynitride (WON), and tantalum oxynitride (TaON).

### Claim 9 (depends on 1)

The method of claim 1, wherein the interconnection layer is formed in a plate shape.

### Claim 10 (depends on 1)

The method of claim 1, further comprising forming a multi-stack structure including at least one cell having the same structure as a cell formed below the interconnection layer.

### Claim 11

A method of manufacturing a semiconductor memory device, comprising:
forming a gate cell material layer on a bit line;
etching a portion of the gate cell material layer in a direction perpendicular to a direction that the bit line extends to form a first trench;
forming a spacer insulating layer in the first trench on sidewalls of the gate cell material layer;
forming an oxide layer below the space insulating layer;
forming a first buried insulating layer in the first trench;
removing the spacer insulating layer;
sequentially forming a gate oxide layer and a gate metal layer in a space formed by removing the spacer insulating layer;
removing a portion of the gate oxide layer and the gate metal layer;
forming a second buried insulating layer in a space formed by removing the portion of the gate oxide layer and the gate metal layer;
removing an upper portion of the gate cell material layer;
sequentially forming a lower electrode and a data storage material layer a space formed by removing the upper portion of the gate cell material layer; and
forming an interconnection layer on the data storage material layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the gate cell material layer includes a semiconductor material selected from the group consisting of silicon (Si), silicon germanium (SiGe), germanium (Ge), and gallium arsenide (GaAs).

### Claim 13 (depends on 12)

The method of claim 12, wherein the gate cell material layer includes a semiconductor material selected from the group consisting of an N-doped semiconductor material, a P-doped semiconductor material, and an undoped semiconductor material to form a source, a drain, and a channel in a direction perpendicular to the direction that the bit line extends.

### Claim 14 (depends on 11)

The method of claim 11, further comprising forming a silicide layer using a material selected from titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), platinum (Pt), lead (Pb), molybdenum (Mo) and tantalum (Ta) at an interface between the lower electrode and the gate cell material layer to reduce a contact resistance between the lower electrode and the gate cell material layer.

### Claim 15 (depends on 11)

The method of claim 11, wherein the data storage layer includes a resistive layer for constituting any one selected from the group consisting of a phase-change random access memory (PCRAM), a magnetic random access memory (MRAM), a spin-transfer torque MRAM (STTMRAM), and a polymer random access memory (PoRAM).

### Claim 16 (depends on 15)

The method of claim 15, wherein, when the data storage material layer includes a material for the PCRAM, the data storage material layer includes a material layer selected from tellurium (Te), selenium (Se), germanium (Ge), a compound thereof, and an alloy thereof.

### Claim 17 (depends on 16)

The method of claim 16, wherein the data storage material layer includes a material selected from the group consisting of Te, Se, Ge, bismuth (Bi), Pb, tin (Sn), arsenic (As), sulfur (5), Si, phosphorus (P), oxygen (O), nitrogen (N), a compound thereof, and an alloy thereof.

### Claim 18 (depends on 11)

The method of claim 11, wherein each of the bit line, the gate metal layer, the lower electrode, and the interconnection layer includes at least one of a metal, an alloy, a metal oxinitride, and a conductive carbon compound including tungsten (W), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), and tantalum oxynitride (TaON).

### Claim 19 (depends on 11)

The method of claim 11, wherein the interconnection layer is formed in a plate shape.

### Claim 20 (depends on 11)

The method of claim 11, further comprising forming a multi-stack structure including at least one cell having the same structure as a cell formed below the interconnection layer.

### Claim 21

A method of manufacturing a semiconductor memory device, comprising:
forming a gate cell material layer on a bit line;
patterning the gate cell material layer in a pillar shape;
forming an insulating layer in a bottom portion of a region where the gate cell material layer is removed;
forming a gate oxide layer on an exposed sidewall of the gate cell material layer;
forming a gate metal layer on the gate oxide layer in the region where the gate cell material layer is removed;
forming a first buried insulating layer in the region where the gate cell material layer is removed;
removing a portion of the gate oxide layer and the gate metal layer;
forming a second buried insulating layer in a space formed by removing the gate oxide layer and the gate metal layer;
removing an upper portion of the gate cell material layer;
sequentially forming a lower electrode and a data storage material layer in a space formed by removing the upper portion of the gate cell material layer; and
forming an interconnection layer on the data storage material layer.

### Claim 22 (depends on 21)

The method of claim 21, wherein the gate cell material layer includes a semiconductor material selected from the group consisting of silicon (Si), silicon germanium (SiGe), germanium (Ge), and gallium arsenide (GaAs).

### Claim 23 (depends on 21)

The method of claim 21, wherein the gate cell material layer includes a semiconductor material selected from the group consisting of an N-doped semiconductor material, a P-doped semiconductor material, and an undoped semiconductor material to form a source, a drain, and a channel in a direction perpendicular to the direction that the bit line extends.

### Claim 24 (depends on 21)

The method of claim 21, further comprising forming a silicide layer using a material selected from titanium (Ti), cobalt (Co), nickel (Ni), tungsten (W), platinum (Pt), lead (Pb), molybdenum (Mo) and tantalum (Ta) at an interface between the lower electrode and the gate cell material layer to reduce a contact resistance between the lower electrode and the gate cell material layer.

### Claim 25 (depends on 21)

The method of claim 21, wherein the data storage layer includes a resistive layer for constituting any one selected from the group consisting of a phase-change random access memory (PCRAM), a magnetic random access memory (MRAM), a spin-transfer torque MRAM (STTMRAM), and a polymer random access memory (PoRAM).

### Claim 26 (depends on 25)

The method of claim 25, wherein, when the data storage material layer includes a material for the PCRAM, the data storage material layer includes a material layer selected from tellurium (Te), selenium (Se), germanium (Ge), a compound thereof, and an alloy thereof.

### Claim 27 (depends on 26)

The method of claim 26, wherein the data storage material layer includes a material selected from the group consisting of Te, Se, Ge, bismuth (Bi), Pb, tin (Sn), arsenic (As), sulfur (S), Si, phosphorus (P), oxygen (O), nitrogen (N), a compound thereof, and an alloy thereof.

### Claim 28 (depends on 21)

The method of claim 21, wherein each of the bit line, the gate metal layer, the lower electrode, and the interconnection layer includes at least one of a metal, an alloy, a metal oxinitride, and a conductive carbon compound including tungsten (W), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), and tantalum oxynitride (TaON).

### Claim 29 (depends on 21)

The method of claim 21, wherein the interconnection layer is formed in a plate shape.

### Claim 30 (depends on 31)

The method of claim 31, further comprising forming a multi-stack structure including at least one cell having the same structure as a cell formed below the interconnection layer.

### Claim 31

A semiconductor memory device, comprising:
a bit line extending in a first direction;
a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape;
a lower electrode and a data storage material layer formed on the vertical gate cell; and
an interconnection layer formed on the data storage material layer.

### Claim 32 (depends on 31)

The semiconductor memory device of claim 31, wherein the interconnection layer is formed in a plate shape.

### Claim 33 (depends on 31)

The method of claim 31, further comprising at least one cell having the same structure as a cell formed below the interconnection layer formed above the interconnection layer in a stack.

### Claim 34

A semiconductor memory device, comprising:
a bit line;
a cell structure having a pattern shape formed on the bit line; and
a vertical gate structure formed on a sidewall of the cell structure.

### Claim 35 (depends on 34)

The semiconductor memory device of claim 34, further comprising a data storage material layer formed on the cell structure.

### Claim 36

A semiconductor memory device, comprising:
a first bit line;
a first cell structure formed on the first bit line, wherein a gate electrode structure of the first cell structure is formed on an outer circumference of the first cell structure;
a first data storage material layer formed on the first cell structure;
a common source line formed on the first data storage material layer;
a second cell structure formed on the common source line, wherein a gate electrode structure of the second cell structure is formed on an outer circumference of the second cell structure;
a second data storage material layer formed on the second cell structure; and
a second bit line formed on the second data storage material layer.