# US 2013/0153847 A1 · Resistive memory device and method of manufacturing the same

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- Number: US 2013/0153847 A1
- Document ID: US20130153847A1
- Status: Published application
- Kind: A1
- Application number: 13/483,462
- Filed: 2012-05-30
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: SK hynix Inc.
- Inventors: Nam Kyun PARK; Kang Sik Choi
- Web page: https://patentgrep.com/patent/US20130153847A1

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/82: {the switching components having a common active material layer}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.

## Claims

### Claim 1

A resistive memory device, comprising:
a semiconductor substrate;
a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, wherein each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor;
a common source line electrically connected to the plurality of stacked resistive memory cells; and
a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.

### Claim 2 (depends on 1)

The resistive memory device of claim 1, wherein the switching transistor includes:
an active layer having a line shape and formed on the semiconductor substrate;
a gate electrode formed to overlap a surface of the active layer; and
a source region and a drain region formed in the active layer at opposite sides of the gate electrode, respectively.

### Claim 3 (depends on 2)

The resistive memory device of claim 2, wherein the gate electrode is formed to have a line structure extending in a direction crossing the active layer and surround an upper surface and at least one of lateral surfaces of the active layer.

### Claim 4 (depends on 2)

The resistive memory device of claim 2, wherein the resistive device layer is formed to be in contact with one side of the drain region of the switching transistor.

### Claim 5 (depends on 4)

The resistive memory device of claim 4, wherein the bit line is formed to be electrically connected to the resistive device layer.

### Claim 6 (depends on 4)

The resistive memory device of claim 4, wherein the bit line is formed in parallel to a surface of the semiconductor substrate,
the resistive memory device further comprising a bit line contact unit configured to electrically connect the resistive device layer and the bit line and extend perpendicularly to the surface of the semiconductor substrate.

### Claim 7 (depends on 2)

The resistive memory device of claim 2, wherein the resistive device layer is formed between the source region and the common source line.

### Claim 8 (depends on 2)

The resistive memory device of claim 2, wherein the common source line is formed to extend perpendicularly to a surface of the semiconductor substrate and be in contact with the source regions of the switching transistors of the plurality of stacked resistive memory cells.

### Claim 9 (depends on 2)

The resistive memory device of claim 2, wherein the common source line is formed to be in parallel to a surface of the semiconductor substrate,
the resistive memory device further comprising a conductive plug that extends perpendicularly to the surface of the semiconductor substrate and connects the resistive device layer to the common source line.

### Claim 10 (depends on 1)

The resistive memory device of claim 1, wherein the resistive device layer includes any one selected from the group consisting of a praseodymium calcium manganese oxide (PCMO) layer, a chalcogenide layer, a magnetic layer, a magnetization switching device layer, and a polymer layer.

### Claim 11 (depends on 2)

The resistive memory device of claim 2, further comprising silicide layers formed on surfaces of the source and drain regions.

### Claim 12 (depends on 2)

The resistive memory device of claim 2, wherein the resistive device layer includes a phase-change material,
the resistive memory device further comprising a heating electrode formed between the drain region of the switching transistor and the resistive device layer in each of the plurality of resistive memory cells.

### Claim 13 (depends on 12)

The resistive memory device of claim 12, wherein the resistive device layer is formed in a plug shape to be in contact with the heating electrodes connected to the switching transistors of the plurality of stacked resistive memory cells.

### Claim 14 (depends on 13)

The resistive memory device of claim 13, further comprising an upper electrode surrounded by the resistive device layer and arranged to be electrically connected to the bit line.

### Claim 15 (depends on 5)

The resistive memory device of claim 5, wherein the heating electrode is formed to a thickness lower than a depth of the drain region.

### Claim 16

A resistive memory device, comprising:
a semiconductor substrate;
a pair of first resistive memory cells formed on the semiconductor substrate;
a first interlayer insulating layer formed on the pair of first resistive memory cells;
a pair of second resistive memory cells formed on the first interlayer insulating layer at positions above the pair of first resistive memory cells;
a common source line electrically connected to the first and second resistive memory cells; and
a bit line electrically connected to the first and second resistive memory cells,
wherein each of the first and second resistive memory cells includes a switching transistor and a resistive device layer connected to the switching transistor.

### Claim 17 (depends on 16)

The resistive memory device of claim 16, wherein, in the pairs of the first and second resistive memory cells, each of the resistive device layers is formed to be in contact with a side of a drain of each of the switching transistors.

### Claim 18 (depends on 17)

The resistive memory device of claim 17, further comprising a bit line contact unit penetrating between the pair of first resistive memory cells and between the pair of second resistive memory cells,
wherein the bit line contact unit is connected to the resistive device layers of the switching transistors and the bit line.

### Claim 19 (depends on 18)

The resistive memory device of claim 18, wherein the pair of first resistive memory cells and the pair of second resistive memory cells are symmetrically arranged with respect to the bit line contact unit.

### Claim 20 (depends on 17)

The resistive memory device of claim 17, wherein the common source line is formed perpendicularly to a surface of the semiconductor substrate to be in contact with source regions of the switching transistors of the pairs of stacked first and second resistive memory cells.

### Claim 21 (depends on 16)

The resistive memory device of claim 16, wherein each of the resistive device layers is formed to electrically connect a source region of a respective one of the switching transistors to the common source line.

### Claim 22 (depends on 16)

The resistive memory device of claim 16, wherein the common source line is formed in parallel to a surface of the semiconductor substrate,
the resistive memory device further comprising a conductive plug configured to penetrate between the pair of first resistive memory cells and between the pair of second resistive memory cells and electrically connect source regions of the switching transistors to the common source line.

### Claim 23 (depends on 22)

The resistive memory device of claim 22, wherein the pair of first resistive memory cells and the pair of second resistive memory cells are symmetrically arranged with respect to the conductive plug.

### Claim 24 (depends on 16)

The resistive memory device of claim 16, wherein the resistive device layer is constituted of a phase-change material,
the resistive device layer is formed in a plug shape and penetrates between the pair of first resistive memory cells and between the pair of second resistive memory cells.

### Claim 25 (depends on 24)

The resistive memory device of claim 24, wherein the pair of first resistive memory cells and the pair of second resistive memory cells are symmetrically arranged with respect to the resistive device layer,
the resistive memory device further comprising a heating electrode formed between the resistive device layer and a drain region of each of the switching transistors.

### Claim 26 (depends on 24)

The resistive memory device of claim 24, further comprising an upper electrode surrounded by the resistive device layer to be in contact with the bit line.

### Claim 27

A method of manufacturing a resistive memory device, comprising:
forming a first active layer on a semiconductor substrate;
forming a first switching transistor and a resistive device layer in the first active layer;
forming a first interlayer insulating layer on a structure including the first active layer;
forming a second active layer on the first interlayer insulating layer;
forming a second switching transistor and a resistive device layer in the second active layer;
forming a common source line to be in contact with source regions of the first and second switching transistors;
forming a second interlayer insulating layer on a structure including the common source line;
forming a bit line contact unit to be in contact with the resistive device layers; and
forming a bit line on the second interlayer insulating layer to be connected to the bit line contact unit.