# US 2013/0153846 A1 · Three dimensional memory array adjacent to trench sidewalls

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- Number: US 2013/0153846 A1
- Document ID: US20130153846A1
- Status: Published application
- Kind: A1
- Application number: 13/330,525
- Filed: 2011-12-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: Macronix International Co., Ltd.
- Inventors: Wei-Chih CHIEN; Ming-Hsiu Lee; Shih-Hung Chen
- Web page: https://patentgrep.com/patent/US20130153846A1

## CPC

- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/028: {by conversion of electrode material, e.g. oxidation}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

## Claims

### Claim 1

An integrated circuit device comprising:
a conductive line having first and second sides;
a plurality of levels of a plurality of conductive pads disposed adjacent the first and second sides of the conductive line, the plurality of conductive pads having proximal sides proximal to a corresponding one of the first and second sides of the conductive line;
metal oxide memory elements on the proximal sides of the plurality of conductive pads in the plurality of levels, and in electrical communication with the corresponding ones of the first and second sides of the conductive lines.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, further comprising:
an array of vertical connectors, the vertical connectors in electrical communication with respective conductive pads in the plurality of levels and overlying circuitry.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein at least two of the plurality of conductive pads are stacked such that at least a first conductive pad is disposed above a second conductive pad, and the first conductive pad has a distal side that is disposed closer to the conductive line than the distal side of the second conductive pad, the distal sides of the first and second conductive pads in electrical communication with corresponding ones of the array of vertical connectors.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein the plurality of conductive pads each include a metal layer between one of the metal oxide memory elements and one of the array of vertical connectors.

### Claim 5 (depends on 4)

The integrated circuit device of claim 4, wherein an oxide of the metal layer is a resistive metal oxide memory element, such that the resistive metal oxide memory element is disposed along the proximal side of the metal layers in the conductive pads.

### Claim 6 (depends on 5)

The integrated circuit device of claim 5, wherein the plurality of conductive pads further include a plurality of barrier metal layers in which the metal layer is disposed between at least two of the metal barrier layers.

### Claim 7 (depends on 5)

The integrated circuit device of claim 5, wherein the plurality of conductive pads further include field enhancement structures adjacent to proximal ends of the metal oxide memory elements proximal to the corresponding one of the first and second sidewalls of the trench.

### Claim 8 (depends on 5)

The integrated circuit device of claim 5, wherein an oxide growth barrier layer is disposed between at least one of the metal oxide memory elements and one of the corresponding first and second sides of the conductive line.

### Claim 9 (depends on 5)

The integrated circuit device of claim 5, wherein a drive device layer is disposed between at least one of the metal oxide memory elements and one of the corresponding first and second sides of the conductive line.

### Claim 10 (depends on 2)

The integrated circuit device of claim 2, wherein the overlying circuitry includes word lines coupled to the array of vertical connectors.

### Claim 11 (depends on 1)

The integrated circuit device of claim 1, wherein the conductive line is a bit line.

### Claim 12

A method comprising:
forming a plurality of levels of a plurality of conductive pads adjacent to a first and a second sidewall of a trench, the plurality of conductive pads having proximal sides proximal to a corresponding one of the first and second sidewalls of the trench;
forming a plurality of metal oxide memory elements on the proximal sides of the plurality of conductive pads;
forming a conductive line within the trench such that the conductive line is in electrical communication with the plurality of metal oxide memory elements.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
forming an array of vertical connectors that are in electrical communication with respective conductive pads in the plurality of levels

### Claim 14 (depends on 12)

The method of claim 12, wherein said forming the plurality of levels of the plurality of conductive pads further comprises depositing a plurality of conductive pad layers, the conductive pad layers including a first metal layer between a first barrier metal layer and a second barrier metal layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein said forming the plurality of metal oxide memory elements includes oxidizing a portion of the metal layer to form at least one resistive metal oxide memory element.

### Claim 16 (depends on 12)

The method of claim 12, further including:
forming field enhancement structures adjacent to proximal ends of the metal oxide memory elements proximal to the corresponding one of the first and second sidewalls of the trench.

### Claim 17 (depends on 12)

The method of claim 12, further including:
forming an oxide growth barrier layer along the first and second sidewalls of the trench before forming the plurality of metal oxide memory elements.

### Claim 18 (depends on 12)

The method of claim 12, further including:
forming a drive device layer along the first and second sidewalls of the trench.

### Claim 19 (depends on 13)

The method of claim 13, wherein the step of forming an array of vertical connectors includes the steps of:
forming cavities through material overlying the respective conductive pads;
forming an insulating layer along the sides of the cavities; and,
filling the cavities with at least one conductive material.

### Claim 20 (depends on 13)

The method of claim 13, further including:
forming word lines coupled to the array of vertical connectors.

### Claim 21 (depends on 12)

The method of claim 12, wherein the conductive line is a bit line.