# US 2013/0153751 A1 · Imaging apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0153751 A1 - Document ID: US20130153751A1 - Status: Published application - Kind: A1 - Application number: 13/819,092 - Filed: 2011-08-23 - Published: 2013-06-20 - Earliest claimed: 2010-08-27 - Assignees: Nikon Corporation - Inventors: Tadao Isogai - Web page: https://patentgrep.com/patent/US20130153751A1 ## CPC - H10F 39/804: {Containers or encapsulations} - H04N 25/70: SSIS architectures; Circuits associated therewith - H10F 39/811: {Interconnections} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract An imaging apparatus includes a sensor chip which has pad electrodes, to which electrical signals to be supplied to a pixel array are input, a glass substrate on which first wiring patterns connected to signal lines, to which signals of the pixel array are output, and second wiring patterns connected to pad electrodes are formed, an upper signal processing chip and a lower signal processing chip which have pad electrodes to which signals processed by signal processing circuits are output, and flexible printed boards which have FPC wiring electrically connected to the pad electrodes and FPC wiring electrically connected to the second wiring patterns formed on the glass substrate. ## Claims ### Claim 1 An imaging apparatus comprising: a sensor chip having a pixel array in which a plurality of pixels are arranged to output signals according to incident light to signal lines, and input terminals to which electrical signals to be supplied to the pixel array are input; a substrate which is disposed on the light-receiving surface side of the sensor chip, and on which first wiring patterns electrically connected to the signal lines and second wiring patterns electrically connected to the input terminals are fanned; signal processing chips which have signal processing circuits which process the signals input through the first wiring patterns, and output terminals to which the signals processed by the signal processing circuits are output; and connection boards which have first wiring electrically connected to the output terminals of the signal processing chips and second wiring electrically connected to the second wiring patterns formed on the substrate. ### Claim 2 (depends on 1) The imaging apparatus according to claim 1, wherein the connection boards include extended portions which extend from the substrate body toward the sensor chip, and the extended portions include extended wiring extending from the second wiring. ### Claim 3 (depends on 1) The imaging apparatus according to claim 1, wherein the connection boards are flexible printed boards. ### Claim 4 (depends on 2) The imaging apparatus according to claim 2, wherein the extended portions extend to reach the lateral side of the sensor chip. ### Claim 5 (depends on 2) The imaging apparatus according to claim 2, wherein the extended portions extend to reach both lateral sides of the sensor chip. ### Claim 6 (depends on 1) The imaging apparatus according to claim 1, wherein the second wiring is power lines which supply power to the sensor chip. ### Claim 7 (depends on 1) The imaging apparatus according to claim 1, wherein the second wiring is clock lines which supply clock signals to the sensor chip. ### Claim 8 (depends on 1) The imaging apparatus according to claim 1. wherein the pixel array includes the pixels arranged in a lattice shape along a column direction and a row direction, and the signal processing chips process the signals output from the pixel array in parallel. ### Claim 9 (depends on 1) The imaging apparatus according to claim 1, wherein external connection portions are provided on both sides of the sensor chip in the column direction, the signal processing chips are connected to the external connection portions between the sensor chip and the external connection portions, even-numbered columns of the pixel array are connected to one signal processing chip of the two signal processing chips, and odd-numbered columns of the pixel array are connected to the other signal processing chip. ### Claim 10 (depends on 1) The imaging apparatus according to claim 1, wherein the signal processing chips include a plurality of digital converters which digitally convert electrical signals from the columns of the pixel array. ### Claim 11 An imaging apparatus comprising: a sensor chip having a pixel array in which a plurality of pixels are arranged to output signals according to incident light to signal lines, and input terminals to which electrical signals to be supplied to the pixel array are input; a substrate which is disposed on the light-receiving surface side of the sensor chip, and on which first wiring patterns electrically connected to the signal lines and second wiring patterns electrically connected to the input terminals are formed; signal processing chips which have signal processing circuits which process the signals input through the first wiring patterns, output terminals to which the signals processed by the signal processing circuits are output, and wiring layers which are electrically connected to the second wiring patterns; and external connection portions which have first wiring electrically connected to the output terminals of the signal processing chips and second wiring electrically connected to the second wiring patterns formed on the substrate. ### Claim 12 (depends on 11) The imaging apparatus according to claim 11, wherein the second wiring patterns and the wiring layers are connected in parallel together. ### Claim 13 (depends on 11) The imaging apparatus according to claim 11, wherein the signal processing chips have a plurality of wiring layers, two or more wiring layers are connected in parallel together, and the two or more wiring layers connected in parallel together are connected to the second wiring patterns. ### Claim 14 (depends on 11) The imaging apparatus according to claim 11, wherein the external connection portions are flexible printed boards. ### Claim 15 (depends on 11) The imaging apparatus according to claim 11, wherein the second wiring patterns are power lines which supply power to the sensor chip. ### Claim 16 (depends on 11) The imaging apparatus according to claim 11, wherein the second wiring patterns are clock lines which supply clock signals to the sensor chip. ### Claim 17 (depends on 11) The imaging apparatus according to claim 11, wherein the pixel array includes the pixels arranged in a lattice shape along a column direction and a row direction, and the signal processing chips process the signals output from the pixel array in parallel. ### Claim 18 (depends on 11) The imaging apparatus according to claim 11, wherein the external connection portions are provided on both sides of the sensor chip in the column direction, the signal processing chips are provided between the sensor chip and the external connection portions, even-numbered columns of the pixel array are connected to one signal processing chip of the two signal processing chips, and odd-numbered columns of the pixel array are connected to the other signal processing chip. ### Claim 19 (depends on 11) The imaging apparatus according to claim 11, wherein the signal processing chips include a plurality of digital converters which digitally convert the signals from the columns of the pixel array.