# US 2013/0153280 A1 · Printed circuit board and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0153280 A1 - Document ID: US20130153280A1 - Status: Published application - Kind: A1 - Application number: 13/425,622 - Filed: 2012-03-21 - Published: 2013-06-20 - Earliest claimed: 2011-12-19 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Inventors: Sang Hoon Kim; Going Sik Kim - Web page: https://patentgrep.com/patent/US20130153280A1 ## CPC - H05K 3/107: {by filling grooves in the support with conductive material (H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence)} - H05K 3/4661: {Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387)} - H05K 3/4647: {by applying an insulating layer around previously made via studs} - H05K 2201/0391: Using different types of conductors - H05K 2201/09036: Recesses or grooves in insulating substrate - Y10T 29/49155: Manufacturing circuit on or in base - Y10T 29/49156: with selective destruction of conductive paths - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract Disclosed herein is a printed circuit board including: a substrate; first upper and lower insulating layers covering upper and lower sides of the substrate; a via penetrating the substrate and the first upper and lower insulating layers to form an electrical connection; and second upper and lower insulating layers covering or surrounding the via, wherein the first upper and lower insulating layers or the second upper and lower insulating layers include a general circuit region including general circuit patterns and circuit patterns connected to the via and a microcircuit region including microcircuit patterns having a smaller circuit line width than that of the general circuit region. ## Claims ### Claim 1 A printed circuit board, comprising: a substrate; first upper and lower insulating layers covering upper and lower sides of the substrate; a via penetrating the substrate and the first upper and lower insulating layers to form an electrical connection; and second upper and lower insulating layers covering or surrounding the via, wherein the first upper and lower insulating layers or the second upper and lower insulating to layers include a general circuit region including general circuit patterns and circuit patterns connected to the via, and a microcircuit region including microcircuit patterns having a smaller circuit line width than that of the general circuit region. ### Claim 2 (depends on 1) The printed circuit board according to claim 1, further comprising: a bump disposed on the microcircuit pattern of the microcircuit region, wherein the bump is surrounded by the second upper and lower insulating layers. ### Claim 3 (depends on 1) The printed circuit board according to claim 1, wherein the general circuit region and the microcircuit region are provided on the same layer. ### Claim 4 (depends on 1) The printed circuit board according to claim 1, wherein the substrate is provided on upper and lower sides thereof with inner circuits connected to the via. ### Claim 5 (depends on 1) The printed circuit board according to claim 1, wherein the general circuit region has a circuit line width of more than 10 μm, and a part of the microcircuit pattern of the microcircuit region is buried in the first insulating layer. ### Claim 6 (depends on 2) The printed circuit board according to claim 2, wherein the microcircuit pattern including the bump is provided on one side thereof with a post. ### Claim 7 A method of manufacturing a printed circuit board, comprising: forming inner circuits on upper and lower sides of a substrate and then forming a first via connecting with parts of the inner circuits; forming first insulating layers covering the inner circuits and the first via; forming a second via connected to the first via and penetrating the first insulating layers, a general circuit region including general circuit patterns and circuit patterns connected to the second via, and a microcircuit region including a plurality of microcircuit patterns; and forming second insulating layers covering the first insulating layers. ### Claim 8 (depends on 7) The method according to claim 7, wherein the inner circuits are formed by a SAP (semi-additive process), an MSAP (modified semi-additive process) or a subtractive process. ### Claim 9 (depends on 7) The method according to claim 7, wherein the forming of the circuit region comprises: forming a plurality of trenches on outer surfaces of the first insulating layers; forming an upper blind via hole (BVH) for exposing an upper surface of the first via and/or a lower blind via hole (BVH) for exposing a lower surface of the first via; and forming the microcircuit pattern and a second via by charging the trenches and the upper and lower BVHs with an electroconductive metal. ### Claim 10 (depends on 9) The method according to claim 9, wherein the plurality of trenches are formed using a laser. ### Claim 11 (depends on 9) The method according to claim 9, wherein the microcircuit pattern is formed by charging the trenches with the electroconductive metal, and the second via is formed by charging the BVHs with the electroconductive metal. ### Claim 12 (depends on 9) The method according to claim 9, wherein the forming of the second insulation layers comprises: forming a final via connected with the second via and covered with the second insulating layers; and forming the second insulating layers covering or surrounding the final via or the microcircuit pattern. ### Claim 13 (depends on 7) The method according to claim 7, wherein, in the forming of the second insulation layers, the bump formed on a part of the microcircuit pattern is surrounded by the second insulation layer. ### Claim 14 (depends on 13) The method according to claim 13, wherein a part of the microcircuit pattern provided with the bump is formed into a post.