# US 2013/0153277 A1 · Electrically bonded arrays of transfer printed active components

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- Number: US 2013/0153277 A1
- Document ID: US20130153277A1
- Status: Published application
- Kind: A1
- Application number: 13/638,040
- Filed: 2011-03-22
- Published: 2013-06-20
- Earliest claimed: 2010-03-29
- Assignees: Semprius, Inc.
- Inventors: Etienne Menard; Christopher Bower; Matthew Meitl; Philip Garrou
- Web page: https://patentgrep.com/patent/US20130153277A1

## CPC

- H10D 86/0214: {using temporary substrates}
- H01S 5/02315: Support members, e.g. bases or carriers
- H05K 1/18: structurally associated with non-printed electric components (H05K1/16 takes precedence)
- H05K 3/0058: {Laminating printed circuit boards onto other substrates, e.g. metallic substrates (H05K1/0281 takes precedence)}
- H05K 3/10: in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10F 39/804: {Containers or encapsulations}
- H10F 77/50: Encapsulations or containers (for photovoltaic modules H10F19/80)
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H01S 5/0233: Mounting configuration of laser chips
- H01S 5/02345: Wire-bonding
- H01S 5/0235: Method for mounting laser chips
- H10P 72/7426: {used as a support during build up manufacturing of active devices}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/07131: {Means for applying material, e.g. for deposition or forming coatings}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature}
- H10W 72/07354: {changes in dispositions}
- H10W 72/074: {of anisotropic conductive adhesives}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/324: {Die-attach connectors having multiple side-by-side cores}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/348: {Top-view layouts, e.g. mirror arrays}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/334: {Thermocompression bonding}
- H10W 80/338: {using EM radiation or electron beams, e.g. using lasers}
- H10W 90/00: Package configurations
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T 29/49139: by inserting component lead or terminal into base aperture
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.

## Claims

### Claim 1

An active component array, comprising:
at least one printable electronic component comprising an active layer including at least one active element on a first surface thereof and a conductive element on a second surface thereof opposite the first surface, the conductive element on the second surface being configured to provide an electrical coupling to the at least one active element on the first surface, wherein the at least one electronic component includes a broken portion of a tether adjacent a periphery thereof; and
a target substrate different from the active layer and including one or more electrical contacts on a surface thereof, wherein the at least one electronic component is printed on the target substrate such that the conductive element on the second surface thereof is in contact with a respective one of the electrical contacts on the surface of the substrate.

### Claim 2 (depends on 1)

The array of claim 1, wherein the tether is configured to releasably adhere the at least one electronic component to an anchor portion of the active layer on a source substrate.

### Claim 3 (depends on 2)

The array of claim 2, wherein the at least one electronic component comprises a plurality of electronic components printed on the target substrate, and wherein, in each of the electronic components, the first surface is configured to be adhered to a stamp to transfer the respective electronic component from the source substrate to the target substrate.

### Claim 4 (depends on 1)

The array of claim 1, further comprising:
an adhesive layer between the second surface of the at least one electronic component and the surface of the target substrate.

### Claim 5 (depends on 4)

The array of claim 4, wherein the adhesive layer comprises a conductive layer between the conductive element of the at least one electronic component and the respective one of the electrical contacts.

### Claim 6 (depends on 5)

The array of claim 5, wherein the adhesive layer comprises a material configured to transition between a nonconductive state and a conductive state responsive to curing thereof.

### Claim 7 (depends on 5)

The array of claim 5, wherein the adhesive layer comprises a eutectic layer, a conductive film, and/or conductive nano-particles.

### Claim 8 (depends on 1)

The array of claim 1, wherein the at least one electronic component includes a via extending therethrough from the first surface to the second surface, and wherein the conductive element extends through the via from the at least one active component on the first surface to the second surface.

### Claim 9 (depends on 8)

The array of claim 8, wherein the conductive element protrudes from the second surface.

### Claim 10 (depends on 1)

The array of claim 1, wherein the conductive element extends from the at least one active component on the first surface to the second surface around a periphery of the active layer.

### Claim 11 (depends on 1)

The array of claim 1, wherein the conductive element is a diode comprising a first doped layer and a second doped layer having a conductivity type opposite that of the first doped layer.

### Claim 12 (depends on 1)

The array of claim 1, wherein the target substrate includes conductive traces thereon, and wherein ones of the conductive traces are coupled to ones of the electrical contacts.

### Claim 13 (depends on 1)

The array of claim 1, wherein the target substrate comprises a a flexible and/or a polymer substrate.

### Claim 14 (depends on 12)

The array of claim 12, wherein the active layer comprises a crystalline, microcrystalline, polycrystalline, or amorphous semiconductor layer.

### Claim 15 (depends on 1)

The array of claim 1, wherein the target substrate including the at least one electronic component printed thereon defines a surface mount package for a chip-level device.

### Claim 16

A method of fabricating an active component array, the method comprising:
providing at least one printable electronic component comprising an active layer including at least one active element on a first surface thereof and a conductive element on a second surface thereof opposite the first surface, the conductive element on the second surface being configured to provide an electrical coupling to the at least one active element on the first surface, wherein the at least one electronic component includes a broken portion of a tether adjacent a periphery thereof; and
printing the at least one electronic component on a target substrate different from the active layer and including one or more electrical contacts on a surface thereof such that the conductive element on the second surface of the at least one electronic component is in contact with a respective one of the electrical contacts.

### Claim 17 (depends on 16)

The method of claim 16, wherein the tether is configured to releasably adhere the at least one electronic component to an anchor portion of the active layer on a source substrate.

### Claim 18 (depends on 17)

The method of claim 17, wherein the at least one electronic component comprises a plurality of electronic components, and wherein printing comprises:
providing the plurality of electronic components releasably adhered to the source substrate by respective tethers;
pressing a stamp on the source substrate to break the respective tethers and adhere the first surface of each of the electronic components to the stamp;
aligning the stamp including the plurality of electronic components thereon with the electrical contacts on the surface of the target substrate;
pressing the stamp on the target substrate such that the conductive element on the second surface of each of the electronic components contacts a respective one of the electrical contacts on the surface of the target substrate; and
separating the stamp from the target substrate to print the plurality of electrical components thereon.

### Claim 19 (depends on 18)

The method of claim 18, wherein providing the plurality of electronic components comprises:
providing the source substrate including a sacrificial layer thereon and the active layer on the sacrificial layer;
processing the active layer to define the plurality of electronic components respectively including the at least one active element on the first surface thereof, respective trenches extending around each of the electronic components, and the respective tethers connecting each of the electronic components to respective anchor portions of the active layer; and
removing portions of the sacrificial layer between the plurality of electronic components and the source substrate such that the plurality of electronic components are releasably adhered to the source substrate by the respective tethers.

### Claim 20 (depends on 18)

The method of claim 18, wherein pressing the stamp on the target substrate is preceded by:
providing an adhesive layer between the second surface of each of the electronic components and the surface of the target substrate.

### Claim 21 (depends on 20)

The method of claim 20, wherein the adhesive layer comprises a conductive layer provided between the conductive element of each of the electronic components and the respective one of the electrical contacts on the target substrate.

### Claim 22 (depends on 21)

The method of claim 21, wherein separating the stamp from the target substrate is preceded by:
curing the adhesive layer to adhere the plurality of electronic components to the target substrate,
wherein an adhesive strength of the adhesive layer is greater than that used to adhere the first surface of each of the electronic components to the stamp.

### Claim 23 (depends on 22)

The method of claim 22, wherein the adhesive layer comprises a material configured to transition between a nonconductive state and a conductive state responsive to the curing thereof.

### Claim 24 (depends on 23)

The method of claim 23, wherein curing comprises selectively irradiating portions of the adhesive layer through the target substrate, the stamp, and/or the electronic components using light, heat, and/or electromagnetic energy.

### Claim 25 (depends on 22)

The method of claim 22, wherein the adhesive layer comprises a eutectic layer, an anisotropic conductive film, and/or conductive nano-particles.

### Claim 26 (depends on 25)

The method of claim 25, wherein the conductive nano-particles are provided in a colloid, and further comprising:
depositing the colloid on the surface of the target substrate using an inkjet dispenser or micro-dispenser to define the adhesive layer.

### Claim 27 (depends on 18)

The method of claim 18, wherein each of the electrical contacts includes a eutectic layer, and further comprising:
reflowing the eutectic layer such that the conductive element on the second surface of each of the electronic components is in contact with the respective one of the electrical contacts

### Claim 28 (depends on 16)

The method of claim 16, wherein the at least one electronic component includes a via extending therethrough from the first surface to the second surface, and wherein the conductive element extends through the via from the at least one active component on the first surface to the second surface.

### Claim 29 (depends on 16)

The method of claim 16, wherein the conductive element extends from the at least one active component on the first surface to the second surface around a periphery of the active layer.

### Claim 30 (depends on 16)

The method of claim 16, wherein the conductive element is a diode comprising a first doped layer and a second doped layer having a conductivity type opposite that of the first doped layer.

### Claim 31 (depends on 16)

The method of claim 16, wherein the target substrate comprises a
a flexible and/or a polymer substrate, and wherein the active layer comprises a crystalline, microcrystalline, polycrystalline, or amorphous semiconductor layer.

### Claim 32 (depends on 16)

The method of claim 16, wherein the at least one electronic component comprises at least one active-matrix pixel controller, light-emitting diode, photo-diode, edge laser, or photovoltaic element.